Vol 1

Electrical Specifications
94 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
Notes:
1. SSC is Spread Spectrum Clocking. The processor core clock frequency is derived from BCLK{0/1}. The system reference clock
to processor core clock ratio is determined during initialization.
2. Ideal Period Nominal: This is as an ideal reference target (0 ppm) to use for calculating the rest of the period measurement
values.
3. 0.1-second Measurement Window (frequency counter): A valuable measurement done using a frequency counter to
determine near DC average frequency (filtering out all jitter including SSC and cycle to cycle). This is used to determine if the
system has a frequency static offset caused usually by incorrect crystal, crystal loading, or incorrect clock configuration.
4. 1.0-ms Measurement Window (scope): This measurement is only used in conjunction with clock post processing software
(for example, Jit3 Advanced) with “filters = LPF 3RD order 1-MHz pole” to filter out high frequency jitter (FM) and shows the
underlying SSC profile. The numbers here bound the SSC Min/Max excursions (SSC magnitude).
5. 1 Clock (No Filter): Any 1 Period measured with a scope. It is measured on a real time Oscilloscope using no filters, a simple
period measurement (or a Jit3 period measurement which is more accurate), and provides absolute Min/Max timing
information.
SSC On 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns
Table 6-25. SMBus Signal AC Specifications
Symbol Parameter Min Max Unit Figure Notes
1,2
1. These parameters are based on design characterization and are not tested.
2. All AC timings for the SMBus signals are referenced at V
IL_MAX
or V
IL_MIN
and measured at the processor pins.
Transmitter and Receiver Timings
F
SMB
SMBCLK Frequency 10 100 kHz
TCK SMBCLK Period 10 100 uS
t
LOW
SMBCLK High Time 4 uS 6-16
t
HIGH
SMBCLK Low Time 4.7 uS 6-16
t
R
SMBus Rise Time 1 uS 6-16
3
3. Rise time is measured from (V
IL_MAX
- 0.15V) to (V
IH_MIN
+ 0.15V). Fall time is measured from (0.9 * V
CC
) to (V
IL_MAX
- 0.15V).
t
F
SMBus Fall Time 0.3 uS 6-16
3
t
SU;DAT
SMBus Input Setup Time 250 ns 6-16
t
HD;DAT
SMBus Input Hold Time 300 ns 6-16
t
BUF
Bus Free Time between Stop and Start Condition 4.7 uS 6-16
4 5
4. Minimum time allowed between request cycles.
5. Following a write transaction, an internal write cycle time of 10 ms must be allowed before starting the next transaction.
t
HD;STA
Hold Time after Repeated Start Condition 4.0 uS 6-16
t
SU;STA
Repeated Start Condition Setup Time 4.7 uS 6-16
t
SU;STO
Stop Condition Setup Time 4.0 uS 6-16
T
5
SMBus Output Valid Delay 0.1 4.5 uS 6-17
SMBus Edge Rate 0.5 1.5 V/ns
6
6. Edge rate measured at 20/80 percent of the signal level with a 50 ohm load.
Table 6-26. JTAG and TAP Signal AC Specifications (Sheet 1 of 2)
T# Parameter Min Typ Max Unit Figure Notes
1,2
T1: TDI, TDO, TMS Pulse Width 1 TCK 6-18
T1: TRST_N Input Pulse Width 2 TCK 6-18
T1: TRST_N Assert Time and TCK Pulse Width 2 TCK 6-18 5
T1: BPM_N[7:0] Input Pulse Width 5 ns 6-18
T1: BPM_N[7:0] Output Pulse Width 10 ns 6-18
T1: EAR_N Output Pulse Width 200 BCLK0 6-18
T3: EAR_N Transition Time (V
IL
to V
IH
)5ns6-18
Table 6-24. BCLK{0/1} Periods with Spread Spectrum Clocking (SSC)