Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 67
Datasheet Volume One, February 2014
Signal Descriptions
THERMTRIP_N Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical
over-temperature conditions: One, the processor junction temperature has reached
a level beyond which permanent silicon damage may occur and Two, the system
memory interface has exceeded a critical temperature limit set by BIOS.
Measurement of the processor junction temperature is accomplished through
multiple internal thermal sensors that are monitored by the Digital Thermal Sensor
(DTS). Simultaneously, the Power Control Unit (PCU) monitors external memory
temperatures via the dedicated SMBus interface to the DIMMs. If any of the DIMMs
exceed the BIOS defined limits, the PCU will signal THERMTRIP_N to prevent
damage to the DIMMs. Once activated, the processor will stop all execution and
shut down all PLLs. To further protect the processor, its core voltage (VCC), VTTA,
VTTQ, VSA, VCCPLL, VVMSE supplies must be removed following the assertion of
THERMTRIP_N. Once activated, THERMTRIP_N remains latched until RESET_N is
asserted. While the assertion of the RESET_N signal may de-assert THERMTRIP_N,
if the processor's junction temperature remains at or above the trip level,
THERMTRIP_N will again be asserted after RESET_N is de-asserted. This signal can
also be asserted if the system memory interface has exceeded a critical
temperature limit set by BIOS.
TSC_SYNC Time stamp counter sync. Used to help align the time stamp counters of a newly
onlined socket to the time stamp counters of existing sockets.
Table 5-11. Miscellaneous Signals (Sheet 1 of 2)
Signal Name Description
BIST_ENABLE Input which allows the platform to enable or disable built-in self test (BIST) on the
processor. This signal is pulled up on the die. This strap is latched during all reset
modes.
BMCINIT Indicates whether Service Processor Boot Mode should be used. Used in
conjunction with FRMAGENT and SOCKET_ID inputs.
• 0: No Service Processor boot. Example boot modes: Local PCH (this processor
hosts a legacy PCH with firmware behind it), Intel QPI Link Boot (for
processors one hop away from the FW agent), or Intel QPI Link Init (for
processors more than one hop away from the firmware agent).
• 1: Service Processor boot. In this mode of operation, the processor performs
the absolute minimum internal configuration and then waits for the Service
Processor to complete its initialization. The socket boots after receiving a “GO”
handshake signal via a firmware scratchpad register.
Needs 240 Ohm pull up/pull down (see boot mode).
DEBUG_EN_N This pin is used to enable certain features used by ITP (for example, probemode).
This pin should be connected to the ITP XDP_PRESENT_N# signal as a security
measure to validate user had physical access to the target platform. Next
generation CPU only. Needs 240 Ohm pull up.
EX_LEGACY_SKT BMCINIT, FRMAGENT, LEGACY_SKT together determine the boot mode (SSP, Intel
QPI Link boot modes, DCF boot), whether local or remote, whether the boot PCH is
attached, whether the socket is legacy and whether port0 is DMI or PCIe (Gen1/2.
With one exception, this input configuration strap indicates to the processor that it
is the legacy socket. The legacy SKT must be strapped for NODE ID 0, via the SKIT-
ID pins. There is only 1 legacy SKT in a partition.
FRMAGENT This input configuration strap indicates to the processor that it is a bootable
firmware agent, that is, that the firmware flash ROM is located behind the local PCH
attached to the processor via the DMI2 interface.This signal is pulled down on the
die, refer to Table 6-6 for details. Needs 240 Ohm pull up/pull down (see boot
mode).
MSMI_N Next generation CPUs only.
PROC_ID[1:0] These outputs can be used by the platform to determine if the installed processor is
an Intel® Xeon® E7v2 processor or a future processor planned for the platform. In
the order of PROC_ID1, PROC_ID0, 00 refers to a Intel® Xeon® E7v2 processor.
There is no connection to the processor silicon for this signal.
NMI Interrupt input. Active high.
PM_FAST_WAKE_N Next generation processors only
PWR_DEBUG_N This is a debug signal for power debug using ITP on next generation processors.
Table 5-10. Processor Asynchronous Sideband Signals (Sheet 2 of 2)
Signal Name Description