Vol 1

Intel® Xeon® Processor E7-8800/4800/2800 v2 Product Family 11
Datasheet Volume One, February 2014
Overview
1 Overview
1.1 Introduction
ALL INFORMATION IN THIS DOCUMENT IS PRELIMINARY AND SUBJECT TO CHANGE.
The Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family Datasheet -
Volume One provides DC and AC electrical specifications, signal integrity, differential
signaling specifications, land and signal definitions, and an overview of additional
processor feature interfaces.
This document is intended to be distributed as a part of the complete EDS document
which consists of three volumes.
The Intel® Xeon® E7 v2 processors are the next generation of 64-bit, multi-core
enterprise processors built on 22-nanometer process technology. Throughout this
document, the Intel® Xeon® E7 v2 processor may be referred to as simply the
processor. Based on the low-power/high performance Intel® Xeon® E7 v2 processor
microarchitecture, the processor is designed for a three-chip platform as opposed to
the previous four-chip platform. The three-chip platform consists of a processor,
memory buffer, and the Platform Controller Hub (PCH) and enables higher
performance, easier validation, and improved x-y footprint. The Intel® Xeon® E7 v2
processor is designed for enterprise workloads and maximum memory expendability.
The Intel® Xeon® E7 v2 processor supports scalable server and HPC platforms of two
or more processors, including “glueless” 8-way platforms.
These processors feature per socket, four Intel® Scalable Memory Interconnect
(Intel® SMI) Gen 2 memory links with speeds up to 2.67 GT/s, three Intel® QuickPath
Interconnect (Intel® QPI) point-to-point links capable of up to 8.0 GT/s, up to 32 lanes
of PCI Express* 3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* 2.0
interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of
physical address space and 48-bit of virtual address space.
Included in this family of processors is integrated I/O (IIO) (such as PCI Express and
DMI2) on a single silicon die. This single die solution is known as a monolithic
processor.
Figure 1-1, Figure 1-2, and Figure 1-3, show the Intel® Xeon® E7 v2 2-socket, 4-
socket and 8 socket platform configurations. The “Legacy CPU” is the boot processor
that is connected to the PCH component, this socket is set to NodeID[0]. In the 4-
socket configuration, the “Remote CPU” is the processor which is not connected to the
Legacy PCH.