Hub Datasheet

90 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.6.20 SB_NERR—System Bus Next Error Register (D0:F1)
Address Offset: 62h
Default Value: 00h
Sticky Yes
Attribute: R/WC
Size: 8 bits
The first system bus error will be stored in the SB_FERR Register. This register stores all future
system bus errors. Multiple bits in this register may be set.
Note: Software must write a 1 to clear bits that are set.
Bits
Default,
Access
Description
7
0b
R/WC
System Bus BINIT# Detected.
0 = No system bus BINIT# detected.
1 = This bit is set on an electrical high-to-low transition (0 to 1) of BINIT#.
6
0b
R/WC
System Bus XERR# Detected.
0 = No system bus XERR# detected.
1 = This bit is set on an electrical high-to-low transition (0 to 1) of XERR# on the system
bus.
5
0b
R/WC
Non-DRAM Lock Error (NDLOCK).
0 = No non-DRAM lock error detected.
1 = The MCH has detected a lock operation to memory space that did not map into
DRAM.
4
0b
R/WC
System Bus Address Above TOM (SBATOM).
0 = No system bus address above TOM detected.
1 = MCH detected an address above DRB7, which is the Top of Memory and above 4 GB.
3
0b
R/WC
System Bus Data Parity Error (SBDPAR).
0 = No system bus data parity error detected.
1 = MCH detected a data parity error on the system bus.
2
0b
R/WC
System Bus Address Strobe Glitch Detected (SBAGL).
0 = No system bus address strobe glitch detected.
1 = MCH detected a glitch on one of the system bus address strobes.
1
0b
R/WC
System Bus Data Strobe Glitch Detected (SBDGL).
0 = No System Bus Data Strobe Glitch detected.
1 = MCH detected a glitch on one of the system bus data strobes.
0
0b
R/WC
System Bus Request/Address Parity Error (SBRPAR).
0 = No system bus request/address parity error detected.
1 = MCH detected a parity error on either the address or request signals of the system
bus.