Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 65
Register Description
6:4
000b
R/W
Mode Select (SMS). These bits select the special operational mode of the DRAM
interface. The special modes are intended for initialization at power up. When this field
is first set to a non-zero value, the DRBs must be set to properly indicate which ranks
are populated, since this information is latched shortly after a non-zero value is first
written. DRBs can be changed later to adjust the rank addresses. A rank that is
indicated as not populated when this field is first written to a non-zero value cannot be
changed to populate later.
It should be noted that some of the MA lines (MA[11:7]) are mapped to two possible HA
bits depending on the installed memory configuration (specifically the page size
programmed for the row in the DRA registers).
000 Post Reset State: In this mode CKEs are deasserted and the DRAMS are in
self-refresh mode. All other combinations of SMS bits results in assertion of one
or more CKEs, except when the device is in C3, or S1 state, where all devices
are in self-refresh, without regard to the value in SMS.
001 NOP Command Enable: All Processor cycles to DRAM result in a NOP
command on the DRAM interface.
010 All Banks Pre-charge Enable: All processor cycles to DRAM result in an “all
banks precharge” command on the DRAM interface.
011 Mode Register Set Enable: All processor cycles to DRAM result in a “mode
register” set command on the DRAM interface. Host address lines are mapped
to SDRAM address lines in order to specify the command sent. Host address
lines [15:3] are mapped to MA[12:0].
100 Extended Mode Register Set Enable: All processor cycles to SDRAM result in
an “extended mode register set” command on the DRAM interface (DDR only).
Host address lines are mapped to SDRAM address lines in order to specify the
command sent. Host address lines [15:3] are mapped to MA[12:0].
101 Reserved.
110 CBR Refresh Enable: In this mode all processor cycles to DRAM result in a
CBR cycle on the SDRAM interface.
111 Normal operation
3
1b
R/W
Registered DIMM Mode Enable (REGD). This bit indicates whether the system has
been populated entirely with registered DIMMs or unbuffered DIMMs. The MCH
supports either registered or unbuffered DIMMs. Note that the specification does not
support mixing of un-buffered DIMMs and registered DIMMs.
0 = All rows are populated with unbuffered DIMMs.
1 = All rows populated with registered DIMMs
2 Reserved
1:0
01b
RO
DRAM Type (DT). This field is used to select between supported SDRAM types. This
is a read only bit in the MCH.
01 = Dual data rate SDRAM
All Others = Reserved
Bits
Default,
Access
Description