Hub Datasheet

Intel

E7505 Chipset MCH Datasheet 59

DRB0 = Total memory in row0 (in 64-MB increments)

DRB1 = Total memory in row0 + row1 (in 64-MB increments)

...

DRB7 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 + row6 + row7 (in 64-MB

increments)

The row referred to by this register is defined by the DIMM chip select used. Double-sided DIMMs

use both Row0 and Row1 (for CS0# and CS1#, even though there is one physical slot for the row.

Single-sided DIMMs use only the even row number, since single-sided DIMMs only support

CS0#. For single-sided DIMMs the value BIOS places in the odd row should equal the same value

as what was placed in the even row field. A row is the 128-b wide interface consisting of two

identical DIMMs.

• Unpopulated rows must be programmed with the value of the last populated row.

• If 16 GB are populated, then the present definition does not allow the full 16 GB to be

accessed. The maximum DRAM addressing is 16 GB–64 MB.

Programming Example:

DIMM1 256 MB in even row, none in odd row (single sided DIMM)

DIMM2 512 MB in even row, 512M in odd row (double sided DIMM)

DIMM3 128 MB in even row, none in odd row (single sided DIMM)

DIMM4 256 MB in even row, 256M in odd row (double sided DIMM)

Address Row Size of Row Accumulative Size Register Value

60h Row 0 (DIMM 1, even) 256 M 256 M 04h

61h Row 1 (DIMM 1, odd) empty 256 M 04h

62h Row 2 (DIMM 2, even) 512 M 768 M 0Ch

63h Row 3 (DIMM 2, odd) 512 M 1280 M 14h

64h Row 4 (DIMM 3, even) 128 M 1408 M 16h

65h Row 5 (DIMM 3, odd) empty 1408 M 16h

66h Row 6 (DIMM 4, even) 256M 1664 M 1A

67h Row 7 (DIMM 4, odd) 256M 1920 M 1E