Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 155
Functional Description
Functional Description 5
This chapter covers the MCH functional units including: System Bus, AGP, DRAM, SMBus,
power management, MCH clocking, MCH system reset and power sequencing.
5.1 System Bus Overview
5.1.1 Source Synchronous Transfers
The MCH is optimized for use with processors based on the Intel
®
NetBurst™ microarchitecture.
The system bus used by the Intel NetBurst microarchitecture processors differs from the P6 micro-
architecture processors system bus in the following ways:
• Source synchronous double-pumped address
• Source synchronous quad-pumped data
• System bus interrupt and sideband delivery
The MCH supports two processor configurations at 533 MHz and 400 MHz. The MCH integrates
AGTL+ termination resistors on all of the AGTL+ signals. The cache line size is 64 bytes. The
address signals are double pumped and a new address can be generated two times for every bus
clock. The data is quad pumped and transfers data four times in one bus clock. Working together,
the 4x data bus and 2x address bus provide a maximum data bus bandwidth of 4.26 GB/s. The
MCH will also run with a System Bus clock of 100 MHz. The MCH supports 36-bit host addresses;
this allows the processor to access the entire 16 GB–64 MB (see note) of the MCH’s memory
address space.
Note: Due to 8-bit register constraints, the maximum usable memory address decode is 15.94 GB
(16 GB–64 MB).
5.1.2 IOQ (In Order Queue) Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions. The MCH also has a
12-deep IOQ; therefore, it does not need to limit the number of simultaneous outstanding
transactions by asserting BNR#.
5.1.3 OOQ (Out of Order Queue) Depth
The MCH supports two outstanding deferred transaction on the System Bus. The two transactions
must target different I/O interfaces as only one deferred transaction can be outstanding to any
single I/O interface at a time.