Hub Datasheet

134 Intel

E7505 Chipset MCH Datasheet

3.9 Hub Interface_B PCI-to-PCI Bridge Error Reporting

Registers (Device 2, Function 1)

The Hub Interface_B (HI_B) error reporting registers are in Device 2 (D2), Function 1 (F1).

Table 3-7 provides the register address map for this device, function.

Warning: Address locations that are not listed the table are considered reserved register locations. Writes to

“Reserved” registers may cause system failure. Reads to “Reserved” registers may return a non-

zero value.

Table 3-7. Hub Interface_B – PCI-to-PCI Bridge Error Reporting Register Address Map (D2:F1)

Address

Offset

Mnemonic Register Name

Default

Value

Access

00–01h VID Vendor Identification 8086h RO

02–03h DID Device Identification 2554h RO

04–05h PCICMD PCI Command 0000h RO, RW

06–07h PCISTS PCI Status 0000h R/WC, RO

08h RID Revision Identification

See register

description

0Ah SUBC Sub Class Code 00h RO

0Bh BCC Base Class Code FFh RO

0Eh HDR Header Type 0000h R/WO

2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO

2E–2Fh SID Subsystem Identification 0000h R/WO

80h HIB_FERR HI_B First Errors 00h R/WC

82h HIB_NERR HI_B Next Errors 00h R/WC

A0h SERRCMD2 SERR Command 00h RO, RW

A2h SMICMD2 SMI Command 00h RO, RW

A4h SCICMD2 SCI Command 00h RO, RW