Hub Datasheet
Intel
®
E7505 Chipset MCH Datasheet 133
Register Description
3.8.20 BCTRL2—Bridge Control Register (D2:F0)
Address Offset: 3Eh
Default Value: 00h
Attribute: RO, R/W
Size: 8 bits
This register provides extensions to the PCICMD2 register that are specific to PCI-to-PCI bridges.
The BCTRL provides additional control for the secondary interface (i.e., HI_B) as well as some
bits that affect the overall behavior of the virtual PCI-to-PCI bridge in the MCH (e.g., VGA
compatible address range mapping).
Bits
Default,
Access
Description
7
0b
RO
Fast Back-to-Back Enable (FB2BEN). Hardwired to 0. The MCH does not generate
fast back-to-back cycles as a master on HI_B.
6
0b
RO
Secondary Bus Reset (SRESET). Hardwired to 0. MCH does not support generation
of reset via this bit on the HI_B.
5
0b
RO
Master Abort Mode (MAMODE). Hardwired to 0. Thus, the MCH, when acting as a
master on HI_B, will drop writes and return all 1s during reads when a Master Abort
occurs.
4 Reserved
3
0b
R/W
VGA Enable (VGAEN). This bit controls the routing of processor-initiated transactions
targeting VGA compatible I/O and memory address ranges.
0 = Disable.
1 = Enable.
NOTE: Only one PCI-to-PCI Bridge VGAEN bits are allowed to be set. This must be
enforced via software.
2
0b
R/W
ISA Enable (ISAEN). This bit modifies the response by the MCH to an I/O access
issued by the processor that target ISA I/O addresses. This applies only to I/O
addresses that are enabled by the IOBASE and IOLIMIT registers.
0 = Disable (default). All addresses defined by the IOBASE and IOLIMIT for processor
I/O transactions will be mapped to HI_B.
1 = MCH does not forward to HI_B any I/O transactions addressing the last 768 bytes
in each 1-KB block, even if the addresses are within the range defined by the
IOBASE and IOLIMIT registers. Instead of going to HI_B, these cycles are
forwarded to HI_A where they can be subtractively or positively claimed by the ISA
bridge.
1
0b
R/W
SERR Enable (2SERRE). This bit enables or disables forwarding of SERR messages
from HI_B to HI_A, where they can be converted into interrupts that are eventually
delivered to the processor.
0 = Disable.
1 = Enable.
0
0b
R/W
Parity Error Response Enable (2PERRE). This bit controls MCH’s response to data
phase parity errors on HI_B.
0 = Address and data parity errors on HI_B are not reported via the MCH HI_A SERR
messaging mechanism. Other types of error conditions can still be signaled via
SERR messaging independent of this bit’s state.
1 = Address and data parity errors on HI_B are reported via the HI_A SERR
messaging mechanism, if further enabled by SERRE2.