Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 129
Register Description
3.8.13 IOBASE2—I/O Base Address Register (D2:F0)
Address Offset: 1Ch
Default Value: F0h
Attribute: R/W, RO
Size: 8 bits
This register control the processor-to-HI_B I/O access routing based on the following formula:
IO_BASE2 ≤ address ≤ IO_LIMIT2
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A11:0 are
treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
3.8.14 IOLIMIT2—I/O Limit Address Register (D2:F0)
Address Offset: 1Dh
Default Value: 00h
Attribute: R/W
Size: 8 bits
This register controls the processor-to-HI_B I/O access routing based on the following formula:
IO_BASE2 ≤ address ≤ IO_LIMIT2
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A11:0 are
assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB
aligned address block.
Bits
Default,
Access
Description
7:4
Fh
R/W
I/O Address Base (IOBASE2). These bits corresponds to A15:12 of the I/O addresses
passed by the device 2 bridge to HI_B
3:0 Reserved
Bits
Default,
Access
Description
7:4
0h
R/W
I/O Address Limit (IOLIMIT2). These bits corresponds to A15:12 of the I/O address
limit of device 2. Devices between this upper limit and IOBASE2 will be passed to HI_B.
3:0 Reserved