Hub Datasheet

114 Intel

E7505 Chipset MCH Datasheet

3.7.24 ERRCMD1—Error Command Register (D1:F0)

Address Offset: 40h

Default Value: 00h

Attribute: R/W

Size: 8 bits

Set by drivers.

Bits

Default,

Access

Description

7:4 Reserved

R/W

SERR on AGP Access Outside of Graphics Aperture (OOGF).

0 = Disable. Reporting of this condition is disabled.

1 = Enable. MCH generates a SERR special cycle over HI_A when an AGP access

occurs to an address outside of the graphics aperture.

R/W

SERR on Invalid AGP Access (IAAF).

0 = Disable. The Invalid AGP Access condition is not reported.

0 = Enable. MCH generates a SERR special cycle over HI_A when an AGP access

occurs to an address outside of the graphics aperture and either to the

640 KB – 1 MB range or above the top of low memory.

R/W

SERR on Invalid Translation Table Entry (ITTEF).

0 = Disable. Reporting of this condition is disabled.

1 = Enable. MCH generates a SERR special cycle over HI_A when an invalid

translation table entry was returned in response to an AGP Access to the graphics

aperture.

R/W

SERR on Receiving Target Abort (SERTA). SERR messaging for Device 1 is globally

enabled in the PCICMD1 register.

0 = Disable. MCH does not assert a SERR message upon receipt of a target abort on

AGP.

1 = Enable. MCH generates an SERR message over the hub interface upon receiving

a target abort on AGP.