Hub Datasheet

112 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7.21 PMLIMIT1—Prefetchable Memory Limit Address Register
(D1:F0)
Address Offset: 26–27h
Default Value: 0000h
Attribute: R/W, RO
Size: 16 bits
This register controls the processor-to-AGP prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20
of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes when read.
This register must be initialized by the configuration software. For the purpose of address decode,
address bits A19:0 are assumed to be FFFFFh. Thus, the top of the defined memory address range
will be at the top of a 1-MB aligned memory block.
Note: Prefetchable memory range is supported to allow segregation by the configuration software
between the memory ranges that must be defined as UC and the ones that can be designated as a
USWC (i.e., prefetchable) from the processor perspective.
3.7.22 CAPPTR—Capabilities Pointer Register (D1:F0)
Address Offset: 34h
Default Value: 60h
Attribute: RO
Size: 8 bits
The CAPPTR register provides an address pointer to the location where the AGP standard registers
are located.
Bits
Default,
Access
Description
15:4
000h
R/W
Prefetchable Memory Address Limit (PMLIMIT). This field corresponds to A31:20 of
the upper limit of the address range passed by bridge device 1 across AGP.
3:0 Reserved
Bits
Default,
Access
Description
7:0
60h
RO
Standard AGP Register Block Pointer (REGBLOK). This pointer indicates to software
where it can find the beginning of the AGP register block.