Datasheet

Datasheet 99
DRAM Controller Registers (D0:F0)
658–65Ah C1CYCTRKRD Channel 1 CYCTRK READ 000000h RW, RO
660–663h C1CKECTRL Channel 1 CKE Control 00000800h
RO, RW/L,
RW
669–66Eh C1REFRCTRL
Channel 1 DRAM Refresh
Control
021830000C
30h
RW, RO
680–687h C1ECCERRLOG Channel 1 ECC Error Log
0000000000
000000h
RO/P, RO
69C–69Fh C1ODTCTRL Channel 1 ODT Control 00000000h RO, RW
A00–A01h EPC0DRB0
EP Channel 0 DRAM Rank
Boundary Address 0
0000h RW, RO
A02–A03h EPC0DRB1
EP Channel 0 DRAM Rank
Boundary Address 1
0000h RW, RO
A04–A05h EPC0DRB2
EP Channel 0 DRAM Rank
Boundary Address 2
0000h RW, RO
A06–A07h EPC0DRB3
EP Channel 0 DRAM Rank
Boundary Address 3
0000h RW, RO
A08–A09h EPC0DRA01
EP Channel 0 DRAM Rank 0,1
Attribute
0000h RW
A0A–A0Bh EPC0DRA23
EP Channel 0 DRAM Rank 2,3
Attribute
0000h RW
A19–A1Ah EPDCYCTRKWRTPRE EPD CYCTRK WRT PRE 0000h RW, RO
A1C–A1Fh EPDCYCTRKWRTACT EPD CYCTRK WRT ACT 00000000h RO, RW
A20–A21h EPDCYCTRKWRTWR EPD CYCTRK WRT WR 0000h RW, RO
A22–A23h EPDCYCTRKWRTREF EPD CYCTRK WRT REF 0000h RO, RW
A24–A26h EPDCYCTRKWRTRD EPD CYCTRK WRT READ 000000h RW
A28–A2Ch EPDCKECONFIGREG
EPD CKE related configuration
registers
00E0000000
h
RW
A30–A33h EPDREFCONFIG EP DRAM Refresh Configuration 40000C30h RW, RO
CD8h TSC1 Thermal Sensor Control 1 00h
RW/L, RW,
RS/WC
CD9h TSC2 Thermal Sensor Control 2 00h RO, RW/L
CDAh TSS Thermal Sensor Status 00h RO
CDC–CDFh TSTTP
Thermal Sensor Temperature
Trip Point
00000000h
RO, RW,
RW/L
CE2h TCO Thermal Calibration Offset 00h
RW/L/K,
RW/L
CE4h THERM1 Thermal Hardware Protection 00h
RW/L, RO,
RW/L/K
CEA–CEBh TIS Thermal Interrupt Status 0000h RO, RWC
CF1–CF1h TSMICMD Thermal SMI Command 00h RO, RW
F14–F17h PMSTS Power Management Status 00000000h RWC/S, RO
Table 9. MCHBAR Register Address Map
Address
Offset
Register Symbol Register Name
Default
Value
Access