Datasheet

DRAM Controller Registers (D0:F0)
66 Datasheet
95h PAM5 Programmable Attribute Map 5 00h RO, RW/L
96h PAM6 Programmable Attribute Map 6 00h RO, RW/L
97h LAC Legacy Access Control 00h
RW, RW/L,
RO
98–99h REMAPBASE Remap Base Address Register 03FFh RO, RW/L
9A–9Bh REMAPLIMIT Remap Limit Address Register 0000h RO, RW/L
9Dh SMRAM System Management RAM Control 02h
RO, RW/L,
RW, RW/L/K
9Eh ESMRAMC
Extended System Management RAM
Control
38h
RW/L, RWC,
RO
A0–A1h TOM Top of Memory 0001h RO, RW/L
A2–A3h TOUUD Top of Upper Usable Dram 0000h RW/L
A4–A7h BSM Base of Stolen Memory 00000000h RW/L, RO
AC–AFh TSEGMB TSEG Memory Base 00000000h RO, RW/L
B0–B1h TOLUD Top of Low Usable DRAM 0010h RW/L, RO
C8–C9h ERRSTS Error Status 0000h RWC/S, RO
CA–CBh ERRCMD Error Command 0000h RW, RO
CC–CDh SMICMD SMI Command 0000h RO, RW
DC–DFh SKPD Scratchpad Data 00000000h RW
E0–EBh CAPID0 Capability Identifier
00000001C1
064000010C
0009h
RO
Table 8. DRAM Controller Register Address Map
Address
Offset
Register
Symbol
Register Name
Default
Value
Access