Datasheet

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
248 Datasheet
8.43 SLOTSTS—Slot Status
B/D/F/Type: 0/6/0/PCI
Address Offset: BA–BBh
Default Value: 0000h
Access: RO, RWC
Size: 16 bits
PCI Express Slot related registers.
Bit Access
Default
Value
Description
15:7 RO 0000000b Reserved
6RO 0b
Presence Detect State (PDS): This bit indicates the presence of an adapter
in the slot, reflected by the logical "OR" of the Physical Layer in-band presence
detect mechanism and, if present, any out-of-band presence detect
mechanism defined for the slot's corresponding form factor. Note that the in-
band presence detect mechanism requires that power be applied to an adapter
for its presence to be detected.
0 = Slot Empty
1 = Card Present in Slot
This register must be implemented on all Downstream Ports that implement
slots. For Downstream Ports not connected to slots (where the Slot
Implemented bit of the PCI Express Capabilities Register is 0b), this bit must
return 1b.
5:4 RO 00b Reserved
3RWC 0b
Detect Changed (PDC): This bit is set when the value reported in Presence
Detect State is changed.
2RO 0b
MRL Sensor Changed (MSC): If an MRL sensor is implemented, this bit is set
when a MRL Sensor state change is detected. If an MRL sensor is not
implemented, this bit must not be set.
1RO 0b
Power Fault Detected (PFD): If a Power Controller that supports power fault
detection is implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware capability, it is
possible that a power fault can be detected at any time, independent of the
Power Controller Control setting or the occupancy of the slot. If power fault
detection is not supported, this bit must not be set.
0RO 0b
Attention Button Pressed (ABP): If an Attention Button is implemented,
this bit is set when the attention button is pressed. If an Attention Button is not
supported, this bit must not be set.