Datasheet

Datasheet 237
Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
8.34 PE_CAP—PCI Express* Capabilities
B/D/F/Type: 0/6/0/PCI
Address Offset: A2–A3h
Default Value: 0142h
Access: RO, RWO
Size: 16 bits
This register indicates PCI Express device capabilities.
8.35 DCAP—Device Capabilities
B/D/F/Type: 0/6/0/PCI
Address Offset: A4–A7h
Default Value: 00008000h
Access: RO
Size: 32 bits
This register indicates PCI Express device capabilities.
Bit Access
Default
Value
Description
15:14 RO 00b Reserved
13:9 RO 00h
Interrupt Message Number (IMN): Not Applicable or Implemented.
Hardwired to 0.
8RWO1b
Slot Implemented (SI):
0 = The PCI Express Link associated with this port is connected to an integrated
component or is disabled.
1 = The PCI Express Link associated with this port is connected to a slot.
7:4 RO 4h
Device/Port Type (DPT): Hardwired to 4h to indicate root port of PCI Express
Root Complex.
3:0 RO 2h
PCI Express Capability Version (PCIECV): Hardwired to 2h to indicate
compliance to the PCI Express Capabilities Register Expansion ECN.
Bit Access
Default
Value
Description
31:16 RO 0000h Reserved
15 RO 1b
Role Based Error Reporting (RBER): This bit indicates that this device
implements the functionality defined in the Error Reporting ECN as required by
the PCI Express 1.1 specification.
14:6 RO 000h Reserved
5RO0b
Extended Tag Field Supported (ETFS): Hardwired to indicate support for 5-
bit Tags as a Requestor.
4:3 RO 00b
Phantom Functions Supported (PFS): Not Applicable or Implemented.
Hardwired to 0.
2:0 RO 000b
Max Payload Size (MPS): Hardwired to indicate 128B max supported payload
for Transaction Layer Packets (TLP).