Datasheet

Intel Manageability Engine Subsystem PCI (D3:F0,F3)
206 Datasheet
7.2.4 KTIER—KT Interrupt Enable
B/D/F/Type: 0/3/3/KT MM/IO
Address Offset: 1h
Default Value: 00h
Access: RW/V, RO/V
Size: 8 bits
This implements the KT Interrupt Enable register. Host access to this address, depends
on the state of the DLAB bit {KTLCR[7]). It must be "0" to access this register. The bits
enable specific events to interrupt the Host. See bit specific definition.
Note: Reset: Host System Reset or D3 -> D0 transition.
7.2.5 KTDLMR—KT Divisor Latch MSB
B/D/F/Type: 0/3/3/KT MM/IO
Address Offset: 1h
Default Value: 00h
Access: RW/V
Size: 8 bits
Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this
bit is 0, Host accesses the KTIER.
This is the standard Serial interface's Divisor Latch register's MSB. This register is only
for software compatibility and does not affect performance of the hardware.
Note: Reset: Host System Reset or D3->D0 transition.
Bit Access
Default
Value
Description
7:4 RO/V 0h Reserved
3RW/V0b
MSR (IER2): When set, this bit enables bits in Modem Status register to cause
an interrupt to host
2RW/V0b
LSR (IER1): When set, this bit enables bits in Receiver Line Status Register to
cause an Interrupt to Host
1RW/V0b
THR (IER1): When set, this bit enables interrupt to be sent to Host when the
tranmit Holding register is empty
0RW/V0b
DR (IER0): When set, Received Data Ready (or Receive FIFO Timeout)
interrupts are enabled to be sent to Host.
Bit Access
Default
Value
Description
7:0 RW/V 00h
Divisor Latch MSB (DLM): Implements the Divisor Latch MSB register of the
Serial Interface.