Datasheet

Intel Manageability Engine Subsystem PCI (D3:F0,F3)
198 Datasheet
7.1.11 CAP—Capabilities Pointer
B/D/F/Type: 0/3/0/PCI
Address Offset: 34h
Default Value: 50h
Access: RO
Size: 8 bits
7.1.12 INTR—Interrupt Information
B/D/F/Type: 0/3/0/PCI
Address Offset: 3C–3Dh
Default Value: 0100h
Access: RO, RW
Size: 16 bits
7.1.13 MGNT—Minimum Grant
B/D/F/Type: 0/3/0/PCI
Address Offset: 3Eh
Default Value: 00h
Access: RO
Size: 8 bits
Bit Access
Default
Value
Description
7:0 RO 50h
Capability Pointer (CP): Indicates the first capability pointer offset. It points
to the PCI power management capability offset.
Bit Access
Default
Value
Description
15:8 RO 01h
Interrupt Pin (IPIN): This field indicates the interrupt pin the HECI host
controller uses. The value of 01h selects INTA# interrupt pin. Note: As HECI is
an internal device in the MCH, the INTA# pin is implemented as an INTA#
message to the ICH.
7:0 RW 00h
Interrupt Line (ILINE): Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this
register.
Bit Access
Default
Value
Description
7:0 RO 00h Grant (GNT): Not implemented, hardwired to 0.