Datasheet

Datasheet 179
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.41 SLOTCAP—Slot Capabilities
B/D/F/Type: 0/1/0/PCI
Address Offset: B4–B7h
Default Value: 00040000h
Access: RWO, RO
Size: 32 bits
PCI Express Slot related registers.
9:4 RO 00h
Negotiated Link Width (NLW): Indicates negotiated link width. This field is
valid only when the link is in the L0, L0s, or L1 states (after link width
negotiation is successfully completed).
01h = x1
10h = x16
All other encodings are reserved.
3:0 RO 0h
Current Link Speed (CLS): This field indicates the negotiated Link speed of the
given PCI Express Link.
0001b = 2.5 GT/s PCI Express Link
All other encodings are reserved. The value in this field is undefined when the
Link is not up.
Bit Access
Default
Value
Description
Bit Access
Default
Value
Description
31:19 RWO 0000h
Physical Slot Number (PSN): Indicates the physical slot number attached to
this Port.
18 RO 1b Reserved
17 RO 0b
Electromechanical Interlock Present (EIP): When set to 1b, this bit
indicates that an Electromechanical Interlock is implemented on the chassis for
this slot.
16:15 RWO 00b
Slot Power Limit Scale (SPLS): Specifies the scale used for the Slot Power
Limit Value.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
If this field is written, the link sends a Set_Slot_Power_Limit message.
14:7 RWO 00h
Slot Power Limit Value (SPLV): In combination with the Slot Power Limit
Scale value, specifies the upper limit on power supplied by slot. Power limit (in
Watts) is calculated by multiplying the value in this field by the value in the Slot
Power Limit Scale field.
If this field is written, the link sends a Set_Slot_Power_Limit message.
6:5 RO 00b Reserved
4RO0b
Power Indicator Present (PIP): When set to 1b, this bit indicates that a
Power Indicator is electrically controlled by the chassis for this slot.
3RO0b
Attention Indicator Present (AIP): When set to 1b, this bit indicates that an
Attention Indicator is electrically controlled by the chassis.