Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 93
Datasheet Volume One, February 2014
Electrical Specifications
Intel® Xeon® E7 v2 processor DC specifications for the Intel® QPI interface are
available in the Intel® QuickPath Interconnect V1.1 Base Electrical Specification and
Validation Methodologies. This document will provide only the processor exceptions to
the Intel® QuickPath Interconnect V1.1 Base Electrical Specification and Validation
Methodologies.
6.9.3.4 Reset and Miscellaneous Signal DC Specifications
For a power-on Reset, RESET_N must stay active for at least 3.5 millisecond after V
CC
and BCLK{0/1} have reached their proper specifications. RESET_N must not be kept
asserted for more than 100 ms while PWRGOOD is asserted. RESET_N must be held
asserted for at least 3.5 millisecond before it is deasserted again. RESET_N must be
held asserted before PWRGOOD is asserted. This signal does not have on-die
termination and must be terminated on the system board.
6.10 AC Specifications
AC specifications are defined at the processor pads, unless otherwise noted.
Therefore, proper simulation is the only means to verify proper timing and signal
quality. Timings specified in this section should be used in conjunction with processor
signal integrity models provided by Intel. Care should be taken to read all notes
associated with each parameter.
6.10.1 Signal AC Specifications
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. For clock jitter specifications, refer to CK420BQ Clock Synthesizer/Driver Specifications.
3. Average Period.
4. The phase drift between reference clocks at the two connected ports, that is the two reference clocks going to the processor.
5. Edge Rate time slopes (V/ns) are measured between +150 mV and -150 mV of the differential output of reference clock.
6. Measurement taken from differential waveform.
7. T
Stable
is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges,
before it is allowed to droop back into the VRB ±100 mV range. See Figure 6-13.
Table 6-23. System Reference Clock (BCLK{0/1}) AC Specifications
Parameter Signal Min Typical Max Unit Figure Notes
1,2
Reference Clock Frequency Differential 100 MHz 3
BCLK Period Differential 10 ns 3
BCLK Edge Rate Differential 1 4 V/ns 6-12 5
T
BCLK-Dutycycle
Differential 40 50 60 % 6-11
T
BCLK-diff-jit
Differential 500 ps 4
V
RB-Diff
Differential -100 100 mV 6-13 6
T
Stable
Differential 500 psec 6-13 7
Table 6-24. BCLK{0/1} Periods with Spread Spectrum Clocking (SSC)
Measurement Window
SSC
State
1 Clock 1 us 0.1s 0.1s 0.1s 1 us 1 Clock
Units
-Jitter c-c
Absolute
PerMin
- SSC
Short-Term
AveMin
- ppm
Long-Term
AveMin
Ideal
Period
Nominal
+ ppm
Long Term
AveMax
+ SSC
Short-Term
AveMax
+Jitter c-c
Absolute
PerMax
SSC Off 9.94900 N/A 9.99900 10.00000 10.00100 N/A 10.05100 ns