Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 75
Datasheet Volume One, February 2014
Electrical Specifications
6.1.9.3.6 SVID Voltage Rail Addressing
The processor addresses 2 different voltage rail control segments within VR12 (VCC
and VSA). The SVID data packet contains a 4-bit addressing code:
Notes:
1. Check with VR vendors for determining the physical address assignment method for their controllers.
2. VR addressing is assigned on a per voltage rail basis.
3. Dual VR controllers will have two addresses with the lowest order address, always being the higher
phase count.
4. For future platform flexibility, the VR controller should include an address offset, as shown with +1
not used.
Figure 6-2. VR Power-State Transitions
PS0
PS2 PS3PS1
Table 6-2. SVID Address Usage
PWM Address (HEX) Intel® Xeon® E7v2
00 V
cc
01 V
sa
02 VMSE MC0
03 +1 not used
04 VMSE MC0
05 +1 not used
06 VMSE MC1
07 +1 not used
08 VMSE MC1