Specification Update

Summary Table of Changes
Intel
®
Xeon
®
Processor E7 v2 Product Family 9
Specification Update January 2015
CF29 XNo Fix
The Integrated Memory Controller does not Enforce CKE High For tXSDLL
DCLKs After Self-Refresh.
CF30 XNo Fix
Intel® QuickData Technology DMA Suspend does not Transition From ARMED
to HALT State.
CF31 XNo Fix
Routing Intel® High Definition Audio Traffic Through VC1 May Result in
System Hang.
CF32 XNo FixPatrol Scrubbing does not Skip Ranks Disabled After DDR Training.
CF33 XNo Fix
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is
Followed by a REP MOVSB or STOSB
CF34 XNo Fix
64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI
Before Any Data is Transferred
CF35 XNo Fix
An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB May
Result EFLAGS.RF Being Incorrectly Set
CF36 XNo FixInstructions Retired Event May Over Count Execution of IRET Instructions
CF37 XNo Fix
An Event May Intervene Before a System Management Interrupt That
Results from IN or INS
CF38 XNo Fix
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for
VEX.vvvv May Produce a #NM Exception
CF39 XNo Fix
An Event May Intervene Before a System Management Interrupt That
Results from IN or INS
CF40 XNo FixSuccessive Fixed Counter Overflows May be Discarded
CF41 XNo Fix
Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM
Exception
CF42 XNo Fix
VM Exits Due to “NMI-Window Exiting” May Not Occur Following a VM Entry
to the Shutdown State
CF43 XNo Fix
Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations
For 64-Bit Linear Addresses
CF44 XNo FixREP MOVSB May Incorrectly Update ECX, ESI, and EDI
CF45 XNo FixPerformance-Counter Overflow Indication May Cause Undesired Behavior
CF46 XNo FixVEX.L is not Ignored with VCVT*2SI Instructions
CF47 XNo Fix
Concurrently Changing the Memory Type and Page Size May Lead to a
System Hang
CF48 XNo FixMCI_ADDR May be Incorrect For Cache Parity Errors
CF49 XNo Fix
Instruction Fetches Page-Table Walks May be Made Speculatively to
Uncacheable Memory
CF50 XNo Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size
or Lead to Memory-Ordering Violations
CF51 XNo Fix
The Processor May Not Properly Execute Code Modified Using a Floating-
Point Store
CF52 XNo Fix
VM Exits Due to GETSEC May Save an Incorrect Value for “Blocking by STI”
in the Context of Probe-Mode Redirection
CF53 XNo FixIA32_MC5_CTL2 is Not Cleared by a Warm Reset
CF54
XNo FixThe Processor May Report a #TS Instead of a #GP Fault
CF55 XNo FixIO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
CF56 XNo FixPerformance Monitor SSE Retired Instructions May Return Incorrect Values
Table 1. Summary Table of Changes (Sheet 2 of 6)
No.
Stepping
Status Errata
D1