Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 55
Specification Update January 2015
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF150 Intel® VT-d Memory Check Error on an Intel® QuickData Technology
Channel May Cause All Other Channels to Master Abort
Problem: An Intel QuickData DMA access to Intel® VT-d protected memory that results in a
protected memory check error may cause master abort completions on all other Intel
QuickData DMA channels.
Implication: Due to this erratum, an error during Intel QuickData DMA access to an Intel® VT-d
protected memory address may cause a master abort on other Intel QuickData DMA
channels.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF151 Writes To Some Control Register Bits Ignore Byte Enable
Problem: Due to this erratum, partial writes to some registers write the full register. The affected
registers are: SADDBGMM2_CFG (Device 12; Function 0-7; Offset 0xA8 and Device 13;
Function 0-6; Offset 0xA8) and LLCERRINJ_CFG (Device 12; Function 0-7; Offset 0xFC
and Device 13; Function 0-6; Offset 0xFC)
Implication: Partial writes of the registers listed above may result in changes to register bytes that
were intended to be unmodified.
Workaround: None identified. Use aligned, full-width DWORD (32-bit) read-modify-write sequencing
to change a portion or portions of the registers listed.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF152 VMSE SVID And SDID CSR Writes Do Not Behave as Expected
Problem: SVID and SDID (Bus 1; Device 17,31; Functions 0-7; Offsets 0x2C and 0x2E) registers
implement write-once registers within their configuration space. Due to this erratum,
write accesses to either of these registers individually, with double-word sized
accesses, may prevent any further update to the other register.
Implication: Writes to SVID and SDID registers may not work as intended.
Workaround: Writes to the SVID and SDID registers must be made with byte or word writes.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF153 Instruction Fetch May Cause Machine Check if Page Size and Memory
Type Was Changed Without Invalidation
Problem: This erratum may cause a machine-check error (IA32_MCi_STATUS.MCACOD=0150H)
on the fetch of an instruction that crosses a 4-KByte address boundary. It applies only
if (1) the 4-KByte linear region on which the instruction begins is originally translated
using a 4-KByte page with the WB memory type; (2) the paging structures are later
modified so that linear region is translated using a large page (2-MByte, 4-MByte, or 1-
GByte) with the UC memory type; and (3) the instruction fetch occurs after the paging-
structure modification but before software invalidates any TLB entries for the linear
region.
Implication: Due to this erratum an unexpected machine check with error code 0150H may occur,
possibly resulting in a shutdown. Intel has not observed this erratum with any
commercially available software.
Workaround: Software should not write to a paging-structure entry in a way that would change, for
any linear address, both the page size and the memory type. It can instead use the
following algorithm: first clear the P flag in the relevant paging-structure entry (e.g.,
PDE); then invalidate any translations for the affected linear addresses; and then
modify the relevant paging-structure entry to set the P flag and establish the new page
size and memory type.