Specification Update

Errata
54 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF145 PCIe* Type 1 VDMs May be Silently Dropped
Problem: Due to this erratum, a PCIe Type 1 VDMs (Vendor Defined Message) is silently dropped
unless the vendor ID is the MCTP (Management Component Transport Protocol) value
of 0x1AB4.
Implication: PCIe Type 1 VDMs may be unexpectedly dropped. Intel has not observed this erratum
to impact the operation of any commercially available system.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF146 Writing PCIe* Port 2A DEVCTRL May Have Side Effects When Port 2 is
Bifurcated
Problem: When PCIe port 2 is bifurcated, due to this erratum, a write to DEVCTRL (Bus 0x0,
Device 0x2, Function 0x0, Offset 0x98) for PCIe port 2A may affect the
max_payload_size field (bits[7:5]) in DEVCTRL for port 2B, port 2C, and/or port 2D
(Bus 0x0, Device 0x2, Function 0x1-3, Offset 0x98). This erratum applies only when an
affected max_payload_size field value for port 2B, port 2C, and/or port 2D is different
than the max_payload_size field value written to port 2A’s DEVCTRL.
Implication: The max_payload_size values for port 2B, 2C, and 2D may not match the end point
device and may result in unpredictable system behavior.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF147 Performance Monitor Instructions Retired Event May Not Count
Consistently
Problem: The Performance Monitor Instructions Retired event (Event C0H; Umask 00H) and the
instruction retired fixed counter IA32_FIXED_CTR0 MSR (309H) are used to count the
number of instructions retired. Due to this erratum, certain internal conditions may
cause the counter(s) to increment when no instruction has retired or to intermittently
not increment when instructions have retired.
Implication: A performance counter counting instructions retired may over count or under count.
The count may not be consistent between multiple executions of the same code.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF148 Patrol Scrubbing Doesn’t Skip Ranks Disabled After DDR Training
Problem: If a rank is detected as failed after completing DDR training then BIOS will mark it as
disabled. Disabled ranks are omitted from the OS memory map. Due to this erratum,
a rank disabled after DDR training completes is not skipped by the Patrol Scrubber.
Patrol Scrubbing of the disabled ranks may result in superfluous correctable and
uncorrectable memory error reports.
Implication: Disabling ranks after DDR training may result in the over-reporting of memory errors.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF149 The System May Shut Down Unexpectedly During a Warm Reset
Problem: Certain complex internal timing conditions present when a warm reset is requested can
prevent the orderly completion of in-flight transactions. It is possible under these
conditions that the warm reset will fail and trigger a full system shutdown.
Implication: When this erratum occurs, the system will shut down and all machine check error logs
will be lost.