Specification Update

Errata
50 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF127 RTID_POOL_CONFIG Registers Incorrectly Behave as a Read-Write
Registers
Problem: The RTID_POOL_CONFIG CSRs (Device 12; Function 0-7; Offset ACH and Device 13,
Function 0-6; Offset ACH) were intended to be Read-Only. Due to this erratum, these
registers behave incorrectly as Read-Write.
Implication: Writes to the RTID_POOL_CONFIG CSRs may lead to unexpected results.
Workaround: None identified. Software should write to RTID_POOL_CONFIG_SHADOW CSRs (Device
12; Function 0-7; Offset B0H and Device 13; Function 0-6; Offset B0H) rather than
RTID_POOL_CONFIG CSRs.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF128 Catastrophic Trip Triggered at Lower Than Expected Temperatures
Problem: Catastrophic Trip is intended to provide protection when the temperature of the
processor exceeds a critical threshold by immediately shutting down the processor. Due
to this erratum, the Catastrophic Trip may be triggered well below the critical threshold.
Implication: When this erratum occurs, the processor improperly issues a catastrophic shutdown
causing a system failure.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF129 PCIe* Hot-Plug Slot Status Register May Not Indicate Command
Completed
Problem: The PCIe Base Specification requires a write to the Slot Control register (Offset 18H) to
generate a hot plug command when the downstream port is hot plug capable. Due to
this erratum, a hot plug command is generated only when one or more of the Slot
Control register bits [11:6] are changed.
Implication: Writes to the Slot Control register that leave bits [11:6] unchanged will not generate a
hot plug command and will therefore not generate a command completed event.
Software that expects a command completed event may not behave as expected.
Workaround: It is possible for software to implement a one-second timeout in lieu of receiving a
command completed event.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF130 PCIe* Correctable Error Status Register May Not Log Receiver Error at
8.0 GT/s
Problem: Due to this erratum, correctable PCIe receiver errors may not be logged in the DPE field
(bit 15) of the PCISTS CSR (Bus:0; Device 1,2,3; Function 0-1,0-3,0-3; Offset 6H)
when operating at 8.0 GT/s.
Implication: Correctable receiver errors during 8.0 GT/s operation may not be visible to the OS or
driver software.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF131 Heavy Memory-to-Memory Traffic on DMA Channels During ROL Traffic
May Cause a Machine Check or Hang
Problem: When there is heavy traffic on the DMA channels along with a large volume of ROL
(Raid On Load) traffic and the transfers are aligned to cacheline boundaries, the system
may experience a machine check error with IA32_MCi_STATUS.MCACOD = 400H or
hang.
Implication: Heavy Memory-to-Memory traffic on DMA channels along with ROL traffic may cause a
machine check or system hang.