Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 45
Specification Update January 2015
the compliance patterns should be based on the maximum data rate supported. Due to
this erratum, the port may select an 8GT/s data rate and associated de-emphasis level
during compliance testing mode.
Implication: When doing PCIe load board compliance testing, the DMI port may transmit using
8 GT/s data rate and de-emphasis levels.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF105 PCIe* Device 3 Does Not Log an Error in UNCERRSTS When an Invalid
Sequence Number in an Ack DLLP is Received
Problem: If the processor‘s PCIe device 3 controller receives an invalid sequence number in an
Ack DLLP (Data Link Layer Packet), it is expected to log an uncorrectable error for the
affected port in bit [4] of the UNCERRSTS register (Bus 0; Device 3; Function 3:0;
Offset 14CH). Due to this erratum, no data link protocol error is logged when an invalid
sequence number in an Ack DLLP occurs on PCIe device 3.
Implication: Software that uses this register upon an uncorrectable PCIe error will not be able to
identify this specific error type.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF106 Programmable Ratio Limits For Turbo Mode is Reported as Disabled
Problem: The Programmable Ratio Limits for Turbo Mode in bit 28 of the MSR_PLATFORM_INFO
MSR (CEH) should be 1 but, due to this erratum, it is reported as 0.
Implication: Due to this erratum, software will incorrectly assume it cannot dynamically vary the
factory configured ratio limit values specified in MSR_TURBO_RATIO_LIMIT MSR
(1ADH) and MSR_TURBO_RATIO_LIMIT1 MSR (1AEH).
Workaround: Software should treat the Programmable Ratio Limits for Turbo Mode bit as set.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF107 PCIe* TLPs in Disabled VC Are Not Reported as Malformed
Problem: The PCIe Base Specification requires processors to report a TLP (Transaction Layer
Packet) with a TC (Traffic Class) that is not mapped to any enabled VC (Virtual Channel)
in an Ingress Port as a Malformed TLP. Due to this erratum, a TLP received on the DMI
port that not is mapped to an enabled VC is not reported as a Malformed TLP.
Implication: Receipt of a TLP with an unmapped PCIe TC may lead to completion time out events or
other unexpected system behavior. Intel has not observed this erratum with any
commercially available software or platform.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF108 PCIe* Link May Fail to Train to 8.0 GT/s
Problem: Due to this erratum, with certain 8.0 GT/s-capable link partners, the PCIe link may fail
to train to 8.0 GT/s as requested.
Implication: When this erratum occurs, the PCIe link will enter an infinite speed-change request
loop.
Workaround: A BIOS workaround has been identified. Refer to the Intel® Xeon® Processor E7 v2
Product Family-based Platform CPU/Intel QPI/Memory Reference Code version 1.0 or
later and release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.