Specification Update

Errata
40 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF83 During Package Power States Repeated PCIe* and/or DMI L1
Transitions May Cause a System Hang
Problem: Under a complex set of internal conditions and operating temperature, when the
processor is in a deep power state (package C3, C6 or C7) and the PCIe and/or DMI
links are toggling in and out of L1 state, the system may hang.
Implication: Due to this erratum, the system may hang.
Workaround: None Identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF84 RDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result
Problem: When CPUID.A.EAX[15:8] reports 8 general-purpose performance monitoring counters
per logical processor, RDMSR of IA32_PERFEVTSEL4-7 (MSR 18AH:18DH) may not
return the same value as previously written.
Implication: Software should not rely on the value read from these MSRs. Writing these MSRs
functions as expected.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF85 MONITOR or CLFLUSH on the Local XAPIC's Address Space Results
in Hang
Problem: If the target linear address range for a MONITOR or CLFLUSH is mapped to the local
xAPIC's address space, the processor will hang.
Implication: When this erratum occurs, the processor will hang. The local xAPIC's address space
must be uncached. The MONITOR instruction only functions correctly if the specified
linear address range is of the type write-back. CLFLUSH flushes data from the cache.
Intel has not observed this erratum with any commercially available software.
Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF86 PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always
Operate With 32-bit Length Registers
Problem: In 64-bit mode, using REX.W=1 with PCMPESTRI and PCMPESTRM or VEX.W=1 with
VPCMPESTRI and VPCMPESTRM should support a 64-bit length operation with RAX/
RDX. Due to this erratum, the length registers are incorrectly interpreted as 32-bit
values.
Implication: Due to this erratum, using REX.W=1 with PCMPESTRI and PCMPESTRM as well as
VEX.W=1 with VPCMPESTRI and VPCMPESTRM do not result in promotion to 64-bit
length registers.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF87 Clock Modulation Duty Cycle Cannot Be Programmed to 6.25%
Problem: When programming field T_STATE_REQ of the IA32_CLOCK_MODULATION MSR (19AH)
bits [3:0] to '0001, the actual clock modulation duty cycle will be 12.5% instead of the
expected 6.25% ratio.
Implication: Due to this erratum, it is not possible to program the clock modulation to a 6.25%
duty cycle.
Workaround: None Identified.