Specification Update

Errata
32 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF51 The Processor May Not Properly Execute Code Modified Using a
Floating-Point Store
Problem: Under complex internal conditions, a floating-point store used to modify the next
sequential instruction may result in the old instruction being executed instead of the
new instruction.
Implication: Self- or cross-modifying code may not execute as expected. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified. Do not use floating-point stores to modify code.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF52 VM Exits Due to GETSEC May Save an Incorrect Value for “Blocking by
STI” in the Context of Probe-Mode Redirection
Problem: The GETSEC instruction causes a VM exit when executed in VMX non-root operation.
Such a VM exit should set bit 0 in the interruptibility-state field in the virtual-machine
control structure (VMCS) if the STI instruction was blocking interrupts at the time
GETSEC commenced execution. Due to this erratum, a VM exit executed in VMX non-
root operation may erroneously clear bit 0 if redirection to probe mode occurs on the
GETSEC instruction.
Implication: After returning from probe mode, a virtual interrupt may be incorrectly delivered
prior to GETSEC instruction. Intel has not observed this erratum with any commercially
available software.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF53 IA32_MC5_CTL2 is Not Cleared by a Warm Reset
Problem: IA32_MC5_CTL2 MSR (285H) is documented to be cleared on any reset. Due to this
erratum this MSR is only cleared upon a cold reset.
Implication: The algorithm documented in Software Developer’s Manual, Volume 3, section titled
“CMCI Initialization” or any other algorithm that counts the IA32_MC5_CTL2 MSR being
cleared on reset will not function as expected after a warm reset.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF54 The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF55 IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
Problem: The IO_SMI bit in SMRAM’s location 7FA4H is set to “1” by the CPU to indicate a System
Management Interrupt (SMI) occurred as the result of executing an instruction that
reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by:
• A non-I/O instruction