Specification Update

Errata
28 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF35 An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB
May Result EFLAGS.RF Being Incorrectly Set
Problem: If a REP MOVSB/STOSB is executed and an interrupt is recognized prior to completion
of the first iteration of the string operation, EFLAGS may be saved with RF=1 even
though no data has been copied or stored. The Software Developer’s Manual states that
RF will be set to 1 for such interrupt conditions only after the first iteration is complete.
Implication: Software may not operate correctly if it relies on the value saved for EFLAGS.RF when
an interrupt is recognized prior to the first iteration of a string instruction. Debug
exceptions due to instruction breakpoints are delivered correctly despite this erratum;
this is because the erratum occurs only after the processor has evaluated instruction-
breakpoint conditions.
Workaround: Software whose correctness depends on value saved for EFLAGS.RF by delivery of the
affected interrupts can disable fast-string operation by clearing Fast-String Enable in bit
0 in the IA32_MISC_ENABLE MSR (1A0H).
Status: For the affected steppings, see the “Summary Table of Changes”.
CF36 Instructions Retired Event May Over Count Execution of IRET
Instructions
Problem: Under certain conditions, the performance monitoring event Instructions Retired (Event
C0H, Unmask 00H) may over count the execution of IRET instruction.
Implication: Due to this erratum, performance monitoring event Instructions Retired may over
count.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF37 An Event May Intervene Before a System Management Interrupt That
Results from IN or INS
Problem: If an I/O instruction (IN, INS, OUT, or OUTS) results in an SMI (system-management
interrupt), the processor will set the IO_SMI bit at offset 7FA4H in SMRAM. This
interrupt should be delivered immediately after execution of the I/O instruction so that
the software handling the SMI can cause the I/O instruction to be re-executed. Due to
this erratum, it is possible for another event (for example. a non maskable interrupt) to
be delivered before the SMI that follows the execution of an IN or INS instruction.
Implication: If software handling an affected SMI uses I/O instruction restart, the handler for the
intervening event will not be executed.
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was
triggered by an instruction that read from an I/O port. The SMM handler must not
restart an I/O instruction if the platform has not been configured to generate a
synchronous SMI for the recorded I/O port address.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF38 Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value
for VEX.vvvv May Produce a #NM Exception
Problem: The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid-
Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-Not-
Available) exception.
Implication: Due to this erratum, some undefined instruction encodings may produce a #NM instead
of a #UD exception.
Workaround: Software should always set the vvvv field of the VEX prefix to 1111b for instances of
the VAESIMC and VAESKEYGENASSIST instructions.
Status: For the affected steppings, see the “Summary Table of Changes”.