Datasheet

Datasheet 7
6.43 SLOTSTS—Slot Status...................................................................................... 182
6.44 RCTL—Root Control ......................................................................................... 183
6.45 RSTS—Root Status.......................................................................................... 184
6.46 PELC—PCI Express Legacy Control..................................................................... 184
6.47 VCECH—Virtual Channel Enhanced Capability Header ........................................... 185
6.48 PVCCAP1—Port VC Capability Register 1............................................................. 185
6.49 PVCCAP2—Port VC Capability Register 2............................................................. 186
6.50 PVCCTL—Port VC Control.................................................................................. 186
6.51 VC0RCAP—VC0 Resource Capability................................................................... 187
6.52 VC0RCTL—VC0 Resource Control....................................................................... 188
6.53 VC0RSTS—VC0 Resource Status........................................................................ 189
6.54 RCLDECH—Root Complex Link Declaration Enhanced............................................ 189
6.55 ESD—Element Self Description.......................................................................... 190
6.56 LE1D—Link Entry 1 Description ......................................................................... 190
6.57 LE1A—Link Entry 1 Address.............................................................................. 191
6.58 PESSTS—PCI Express* Sequence Status ............................................................ 191
7 Intel Manageability Engine Subsystem PCI (D3:F0,F3).......................................... 193
7.1 HECI Function in ME Subsystem (D3:F0) ............................................................ 193
7.1.1 ID—Identifiers ..................................................................................... 194
7.1.2 CMD—Command .................................................................................. 194
7.1.3 STS—Device Status.............................................................................. 195
7.1.4 RID—Revision ID.................................................................................. 195
7.1.5 CC—Class Code.................................................................................... 195
7.1.6 CLS—Cache Line Size............................................................................ 196
7.1.7 MLT—Master Latency Timer ................................................................... 196
7.1.8 HTYPE—Header Type ............................................................................ 196
7.1.9 HECI_MBAR—HECI MMIO Base Address................................................... 197
7.1.10 SS—Sub System Identifiers ................................................................... 197
7.1.11 CAP—Capabilities Pointer....................................................................... 198
7.1.12 INTR—Interrupt Information.................................................................. 198
7.1.13 MGNT—Minimum Grant......................................................................... 198
7.1.14 MLAT—Maximum Latency...................................................................... 199
7.1.15 HFS—Host Firmware Status................................................................... 199
7.1.16 PID—PCI Power Management Capability ID.............................................. 199
7.1.17 PC—PCI Power Management Capabilities ................................................. 200
7.1.18 PMCS—PCI Power Management Control And Status................................... 200
7.1.19 MID—Message Signaled Interrupt Identifiers............................................ 201
7.1.20 MC—Message Signaled Interrupt Message Control..................................... 201
7.1.21 MA—Message Signaled Interrupt Message Address.................................... 202
7.1.22 MUA—Message Signaled Interrupt Upper Address (Optional) ...................... 202
7.1.23 MD—Message Signaled Interrupt Message Data........................................ 202
7.1.24 HIDM—HECI Interrupt Delivery Mode...................................................... 203
7.2 KT IO/ Memory Mapped Device Specific Registers [D3:F3].................................... 204
7.2.1 KTRxBR—KT Receive Buffer .................................................................. 204
7.2.2 KTTHR—KT Transmit Holding ................................................................ 205
7.2.3 KTDLLR—KT Divisor Latch LSB .............................................................. 205
7.2.4 KTIER—KT Interrupt Enable .................................................................. 206
7.2.5 KTDLMR—KT Divisor Latch MSB ............................................................. 206
7.2.6 KTIIR—KT Interrupt Identification .......................................................... 207
7.2.7 KTFCR—KT FIFO Control ....................................................................... 208
7.2.8 KTLCR—KT Line Control ....................................................................... 209
7.2.9 KTMCR—KT Modem Control .................................................................. 210
7.2.10 KTLSR—KT Line Status ......................................................................... 211
7.2.11 KTMSR—KT Modem Status ................................................................... 212