Datasheet

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
256 Datasheet
8.55 ESD—Element Self Description
B/D/F/Type: 0/6/0/MMR
Address Offset: 144–147h
Default Value: 03000100h
Access: RO, RWO
Size: 32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit Access
Default
Value
Description
31:24 RO 03h
Port Number (PN): This field specifies the port number associated with this
element with respect to the component that contains this element. This port
number value is used by the egress port of the component to provide arbitration
to this Root Complex Element.
23:16 RWO 00h
Component ID (CID): This field indicates the physical component that contains
this Root Complex Element.
15:8 RO 01h
Number of Link Entries (NLE): This field indicates the number of link entries
following the Element Self Description. This field reports 1 (to Egress port only
as we don't report any peer-to-peer capabilities in our topology).
7:4 RO 0h Reserved
3:0 RO 0h Element Type (ET): This field indicates Configuration Space Element.