Datasheet

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
216 Datasheet
8.2 DID1—Device Identification
B/D/F/Type: 0/6/0/PCI
Address Offset: 2–3h
Default Value: 29F9h
Access: RO
Size: 16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
8.3 PCICMD1—PCI Command
B/D/F/Type: 0/6/0/PCI
Address Offset: 4–5h
Default Value: 0000h
Access: RO, RW
Size: 16 bits
Bit Access
Default
Value
Description
15:8 RO 29h
Device Identification Number (DID1(UB)): Identifier assigned to the MCH
device #6 (virtual PCI-to-PCI bridge, PCI Express port).
7:4 RO Fh
Device Identification Number (DID1(HW)): Identifier assigned to the MCH
device #6 (virtual PCI-to-PCI bridge, PCI Express port).
3:0 RO 9h
Device Identification Number (DID1(LB)): Identifier assigned to the MCH
device #6 (virtual PCI-to-PCI bridge, PCI Express port).
Bit Access
Default
Value
Description
15:11 RO 00h Reserved
10 RW 0b
INTA Assertion Disable (INTAAD):
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages. Any INTA
emulation interrupts already asserted must be de-asserted when this bit is
set.
This bit only affects interrupts generated by the device (PCI INTA from a PME
event) controlled by this command register. It does not affect upstream MSIs,
upstream PCI INTA-INTD assert and deassert messages.
9RO0b
Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented. Hardwired
to 0.