Datasheet

Intel Manageability Engine Subsystem PCI (D3:F0,F3)
212 Datasheet
7.2.11 KTMSR—KT Modem Status
B/D/F/Type: 0/3/3/KT MM/IO
Address Offset: 6h
Default Value: 00h
Access: RO, RO/CR
Size: 8 bits
The functionality of the Modem is emulated by the FW. This register provides the status
of the current state of the control lines from the modem.
Note: Reset: Host system Reset or D3->D0 transition.
7.2.12 KTSCR—KT Scratch
B/D/F/Type: 0/3/3/KT MM/IO
Address Offset: 7h
Default Value: 00h
Access: RW
Size: 8 bits
This register has no affect on hardware. This is for the programmer to hold data
temporarily.
Note: Reset: Host system reset or D3->D0 transition
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Bit Access
Default
Value
Description
7RO0b
Data Carrier Detect (DCD): In Loop Back mode this bit is connected by
hardware to the value of MCR bit 3
6RO0b
Ring Indicator (RI): In Loop Back mode this bit is connected by hardware to
the value of MCR bit 2.
5RO0b
Data Set Ready (DSR): In Loop Back mode this bit is connected by hardware
to the value of MCR bit 0.
4RO0b
Clear To Send (CTS): In Loop Back mode this bit is connected by hardware to
the value of MCR bit 1.
3RO/CR0b
Delta Data Carrier Detect (DDCD): This bit is set when bit 7 is changed. This
bit is cleared by hardware when the MSR register is being read by the HOST
driver.
2RO/CR0b
Trailing Edge of Read Detector (TERI): This bit is set when bit 6 is changed
from 1 to 0. This bit is cleared by hardware when the MSR register is being read
by the Host driver.
1RO/CR0b
Delta Data Set Ready (DDSR): This bit is set when bit 5 is changed. This bit is
cleared by hardware when the MSR register is being read by the Host driver.
0RO/CR0b
Delta Clear To Send (DCTS): This bit is set when bit 4 is changed. This bit is
cleared by hardware when the MSR register is being read by the Host driver.
Bit Access
Default
Value
Description
7:0 RW 00h Scratch Register Data (SCRD):