Datasheet

DRAM Controller Registers (D0:F0)
130 Datasheet
21:18 RW 0000b
DRAM Refresh High Watermark (REFHIGHWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_high flag is set.
0000 = 0
0001 = 1
.......
1000 = 8
17:14 RW 0000b
DRAM Refresh Low Watermark (REFLOWWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_low flag is set.
0000 = 0
0001 = 1
.......
1000 = 8
13:0 RW
00110000
110000b
Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a
value that will provide 7.8 us at mclk frequency.
At various mclk frequencies, this results in the following values:
400 Mhz -> C30 hex (Default Value)
533 Mhz -> 104B hex
666 Mhz -> 1450 hex
Bit Access
Default
Value
Description