Datasheet

DRAM Controller Registers (D0:F0)
104 Datasheet
5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 208–209h
Default Value: 0000h
Access: RW/L
Size: 16 bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch0 Rank0, 1: 208h–209h
Ch0 Rank2, 3: 20Ah–20Bh
Ch1 Rank0, 1: 608h–609h
Ch1 Rank2, 3: 60Ah–60Bh
DRA[6:0] = "00" means cfg0, DRA[6:0] ="01" means cfg1.... DRA[6:0] = "09" means
cfg9 and so on.
DRA[7] indicates whether it's an 8 bank config or not. DRA[7] = 0 means 4 bank,
DRA[7] = 1 means 8 bank.
Table 10. DRAM Rank Attribute Register Programming
Config Tech DDRx Depth Width Row Col Bank Row Size
Page
Size
0 256Mb 2 32M 8 13 10 2 256 MB 8k
1 256Mb 2 16M 16 13 9 2 128 MB 4k
2 512Mb 2 64M 8 14 10 2 512 MB 8k
3 512Mb 2 32M 16 13 10 2 256 MB 8k
4 512Mb 3 64M 8 13 10 3 512 MB 8k
5 512Mb 3 32M 16 12 10 3 256 MB 8k
6 1 Gb 2,3 128M 8 14 10 3 1 GB 8k
7 1 Gb 2,3 64M 16 13 10 3 512 MB 8k
Bit Access
Default
Value
Description
15:8 RW/L 00h
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This register defines DRAM
pagesize/number-of-banks for rank1 for given channel
.
See table in register description for programming.
This register is locked by ME stolen Memory lock.
7:0 RW/L 00h
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This register defines DRAM
page size/number-of-banks for rank0 for given channel.
See table in register description for programming.
This register is locked by ME stolen Memory lock.