Datasheet

Processor Configuration Registers
82 Datasheet, Volume 2
2.5.35 SCICMD—SCI Command Register
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
2.5.36 SKPD—Scratchpad Data Register
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
B/D/F/Type: 0/0/0/PCI
Address Offset: CE–CFh
Reset Value: 0000h
Access: RW
Size: 16 bits
BIOS Optimal Default 0000h
Bit Attr
Reset
Value
RST/
PWR
Description
15:2 RO 0h Reserved
1 RW 0b Uncore
SCI on Multiple-Bit DRAM ECC Error (DMESCI)
1 = The Host generates an SCI DMI message when it detects a
multiple-bit error reported by the DRAM controller.
0 = Reporting of this condition using SCI messaging is disabled.
For systems not supporting ECC, this bit must be disabled.
0 RW 0b Uncore
SCI on Single-bit ECC Error (DSESCI)
1 = The Host generates an SCI DMI special cycle when the DRAM
controller detects a single bit error.
0 = Reporting of this condition using SCI messaging is disabled.
For systems that do not support ECC, this bit must be disabled.
B/D/F/Type: 0/0/0/PCI
Address Offset: DC–DFh
Reset Value: 0000_0000h
Access: RW
Size: 32 bits
Bit Attr
Reset
Value
RST/
PWR
Description
31:0 RW
0000_000
0h
Uncore
Scratchpad Data (SKPD)
1 DWORD of data storage.