Datasheet
Processor Configuration Registers
80 Datasheet, Volume 2
2.5.32 ERRSTS—Error Status Register
This register is used to report various error conditions using the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a '1' to it.
B/D/F/Type: 0/0/0/PCI
Address Offset: C8–C9h
Reset Value: 0000h
Access: RW1CS
Size: 16 bits
BIOS Optimal Default 0000h
Bit Attr
Reset
Value
RST/
PWR
Description
15:2 RO 0h Reserved
1 RW1CS 0b
Powerg
ood
Multiple-bit DRAM ECC Error Flag (DMERR)
If this bit is set to 1, a memory read data transfer had an
uncorrectable multiple-bit error. When this bit is set, the column,
row, bank, and rank that caused the error, and the error syndrome,
are logged in the ECC Error Log register in the channel where the
error occurred. Once this bit is set, the ECCERRLOGx fields are
locked until the processor clears this bit by writing a 1. Software
uses bits 1:0 to detect whether the logged error address is for a
Single-bit or a Multiple-bit error.
This bit is reset on PWROK.
0 RW1CS 0b
Powerg
ood
Single-bit DRAM ECC Error Flag (DSERR)
If this bit is set to 1, a memory read data transfer had a single-bit
correctable error and the corrected data was returned to the
requesting agent. When this bit is set the column, row, bank, and
rank where the error occurred and the syndrome of the error are
logged in the ECC Error Log register in the channel where the error
occurred. Once this bit is set the ECCERRLOGx fields are locked to
further single-bit error updates until the processor clears this bit by
writing a 1. A multiple bit error that occurs after this bit is set will
overwrite the ECCERRLOGx fields with the multiple-bit error
signature and the DMERR bit will also be set. A single bit error that
occurs after a multi-bit error will set this bit but will not overwrite
the other fields.
This bit is reset on PWROK.