Datasheet

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Datasheet, Volume 2 47

Processor Configuration Registers

81h PAM1 Programmable Attribute Map 1 00h RW

82h PAM2 Programmable Attribute Map 2 00h RW

83h PAM3 Programmable Attribute Map 3 00h RW

84h PAM4 Programmable Attribute Map 4 00h RW

85h PAM5 Programmable Attribute Map 5 00h RW

86h PAM6 Programmable Attribute Map 6 00h RW

87h LAC Legacy Access Control 00h RW

88h RSVD

Reserved

02h

RW-L, RW-KL,

RW-LV, RO

89–8Fh RSVD Reserved 0h RO

90–97h REMAPBASE

Remap Base Address Register 0000_000F_F

FF0_0000h

RW-KL, RW-L

98–9Fh REMAPLIMIT

Remap Limit Address Register 0000_0000_0

000_0000h

RW-KL, RW-L

A0–A7h TOM

Top of Memory 0000_007F_F

FF0_0000h

RW-KL, RW-L

A8–AFh TOUUD

Top of Upper Usable DRAM 0000_0000_0

000_0000h

RW-KL, RW-L

B0–B3h BDSM Base Data of Stolen Memory 0000_0000h RW-KL, RW-L

B4–B7h BGSM Base of GTT stolen Memory 0010_0000h RW-KL, RW-L

B8–BBh TSEGMB TSEG Memory Base 0000_0000h RW-KL, RW-L

BC–BFh TOLUD Top of Low Usable DRAM 0010_0000h RW-KL, RW-L

C0– RSVD Reserved 0h RO

C8–C9h ERRSTS Error Status 0000h RW1CS

CA–CBh ERRCMD Error Command 0000h RW

CC–CDh SMICMD SMI Command 0000h RW

CE–CFh SCICMD SCI Command 0000h RW

D0–DBh RSVD Reserved 0h RO

DC–DFh SKPD Scratchpad Data 0000_0000h RW

E0–E3h RSVD Reserved 0h RO

E4–E7h CAPID0_A

Capabilities A

0000_0000h

RO-FW, RO-

KFW

E8–EBh RSVD Reserved 0000_0000h RO-FW

Table 2-7. PCI Device 0, Function 0 Register Address Map (Sheet 2 of 2)

Address

Offset

Symbol