Datasheet

Processor Configuration Registers
104 Datasheet, Volume 2
2.6.24 BCTRL1—Bridge Control Register
This register provides extensions to the PCICMD register that are specific to PCI-to-PCI
bridges. BCTRL1 provides additional control for the secondary interface (that is, PCI
Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-
PCI Express bridge embedded within the processor (such as, VGA compatible address
ranges mapping).
B/D/F/Type: 0/1/0–2/PCI
Address Offset: 3E–3Fh
Reset Value: 0000h
Access: RW, RO
Size: 16 bits
BIOS Optimal Default 0h
Bit Attr
Reset
Value
RST/
PWR
Description
15:12 RO 0h Reserved
11 RO 0b Uncore
Discard Timer SERR# Enable (DTSERRE)
Not Applicable or Implemented. Hardwired to 0.
10 RO 0b Uncore
Discard Timer Status (DTSTS)
Not Applicable or Implemented. Hardwired to 0.
9 RO 0b Uncore
Secondary Discard Timer (SDT)
Not Applicable or Implemented. Hardwired to 0.
8 RO 0b Uncore
Primary Discard Timer (PDT)
Not Applicable or Implemented. Hardwired to 0.
7 RO 0b Uncore
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hardwired to 0.
6 RW 0b Uncore
Secondary Bus Reset (SRESET)
Setting this bit triggers a hot reset on the corresponding PCI
Express Port. This will force the TXTSSM to transition to the Hot
Reset state (using Recovery) from L0, L0s, or L1 states.
5 RO 0b Uncore
Master Abort Mode (MAMODE)
Does not apply to PCI Express. Hardwired to 0.
4 RW 0b Uncore
VGA 16-bit Decode (VGA16D)
This bit enables the PCI-to-PCI bridge to provide 16-bit decoding of
VGA I/O address precluding the decoding of alias addresses every
1 KB. This bit only has meaning if bit 3 (VGA Enable) of this
register is also set to 1, enabling VGA I/O decoding and forwarding
by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
3 RW 0b Uncore
VGA Enable (VGAEN)
This bit controls the routing of processor-initiated transactions
targeting VGA compatible I/O and memory address ranges. See
the VGAEN/MDAP table in Device 0, offset 97h[0].