Datasheet

4
Features Benefits
I/O Features for Multi-Core Processor Servers
Multiple queues & receive-side scaling
• DMA Engine: enhances data acceleration across the platform (network, chipset,
processor), thereby lowering CPU usage
• Direct Cache Access (DCA): enables the adapter to pre-fetch the data from memory,
thereby avoiding cache misses and improving application response time
MSI-X support
• Minimizes the overhead of interrupts
• Allows load balancing of interrupt handling between multiple cores/CPUs
Low Latency Interrupts
• Based on the sensitivity of the incoming data it can bypass the automatic moderation
of time intervals between the interrupts
Header splits and replication in receive
• Helps the driver to focus on the relevant part of the packet without the need to parse it
Multiple queues: 8 queues per port
• Network packet handling without waiting or buffer overflow providing efficient packet
prioritization
Tx/Rx IP, SCTP, TCP, and UDP checksum offloading
(IPv4, IPv6) capabilities
• Lower processor usage
• Checksum and segmentation capability extended to new standard packet type
Tx TCP segmentation offload (IPv4, IPv6)
• Increased throughput and lower processor usage
• Compatible with large send offload feature (in Microsoft Windows* Server OSs)
Receive and Transmit Side Scaling for Windows*
environment and Scalable I/O for Linux*
environments (IPv4, IPv6, TCP/UDP)
• This technology enables the direction of the interrupts to the processor cores in order
to improve the CPU utilization rate
IPsec Offload
• Offloads IPsec capability onto the adapter instead of the software to significantly
improve I/O throughput and CPU utilization (for Windows* 2008 Server and Vista*)
LinkSec
• A Layer 2 data protection solution that provides encryption and authentication ability
between two individual devices (routers, switches, etc.)
• These adapters are prepared to provide LinkSec functionality when the ecosystem
supports this new technology
Virtualization Features
Virtual Machine Device queues
2
(VMDq)
• Offloads the data sorting functionality from the Hypervisor to the network silicon,
thereby improving data throughput and CPU usage
• Provides QoS feature on the Tx data by providing round robin servicing and preventing
head-of-line blocking
• Sorting based on MAC addresses and VLAN tags
Next-generation VMDq
• Enhanced QoS feature by providing weighted round robin servicing for the Tx data
• Provides loopback functionality, where data transfer between the virtual machines
within the same physical server need not go out to the wire and come back in. This
improves throughput and CPU usage.
• Supports replication of multicast and broadcast data
IPv6 offloading
• Checksum and segmentation capability extended to the new standard packet type
Advanced packet filtering
• 24 exact-matched packets (unicast or multicast)
• 4096-bit hash filter for unicast and multicast frames
• Lower processor usage
• Promiscuous (unicast and multicast) transfer mode support
• Optional filtering of invalid frames
VLAN support with VLAN tag insertion, stripping
and packet filtering for up to 4096 VLAN tags
• Ability to create multiple VLAN segments
PC-SIG SR-IOV Implementation
(8 virtual functions per port)
Note: Requires a virtualization operating system and server
platform that supports SR-IOV and VT-d.
Provides an implementation of the PCI-SIG standard for I/O Virtualization. The physi-
cal configuration of each port is divided into multiple virtual ports. Each virtual port is
assigned to an individual virtual machine directly by bypassing the virtual switch in the
Hypervisor, resulting in near-native performance.