Intel Desktop Board DP965LT Technical Product Specification

1.5 Intel

P965 Express Chipset

The Intel P965 Express chipset consists of the following devices:

• Intel 82P965 Memory Controller Hub (MCH) with Direct Media Interface (DMI)

interconnect

• Intel 82801HB I/O Controller Hub (ICH8) with DMI interconnect

The MCH component provides interfaces to the CPU, memory, PCI Express, and the

DMI interconnect. The ICH8 is a centralized controller for the board’s I/O paths.

For information about Refer to

The Intel P965 Express chipset http://developer.intel.com/

Resources used by the chipset Chapter 2

1.5.1 USB

The board supports up to 10 USB 2.0 ports, supports UHCI and EHCI, and uses UHCI-

and EHCI-compatible drivers.

The ICH8 provides the USB controller for all ports. The port arrangement is as

follows:

• Six ports are implemented with stacked back panel connectors

• Four ports are routed to two separate front panel USB headers



NOTE

Computer systems that have an unshielded cable attached to a USB port may not

meet FCC Class B requirements, even if no device is attached to the cable. Use

shielded cable that meets the requirements for full-speed devices.

For information about Refer to

The location of the USB connectors on the back panel Figure 15, page 51

The location of the front panel USB headers Figure 16, page 52

1.5.2 Serial ATA Interfaces

The board provides six Serial ATA (SATA) connectors, which support one device per

connector.

1.5.2.1 Serial ATA Support

The ICH8’s Serial ATA controller offers six independent Serial ATA ports with a

theoretical maximum transfer rate of 3 Gbits/sec per port. One device can be installed

on each port for a maximum of six Serial ATA devices. A point-to-point interface is

used for host to device connections, unlike Parallel ATA IDE which supports a

master/slave configuration and two devices per channel.

For compatibility, the underlying Serial ATA functionality is transparent to the

operating system. The Serial ATA controller can operate in both legacy and native

modes. In legacy mode, standard IDE I/O and IRQ resources are assigned (IRQ 14