Product guide
Table Of Contents
- Intel® Desktop Board DH57JG Product Guide
- Revision History
- Preface
- Contents
- 1 Desktop Board Features
- 2 Installing and Replacing Desktop Board Components
- Before You Begin
- Installation Precautions
- Installing the I/O Shield
- Installing and Removing the Desktop Board
- Installing and Removing a Processor
- Installing and Removing System Memory
- Installing and Removing PCI Express x16 Graphics Cards
- Connecting Serial ATA (SATA) Cables
- Connecting to the Internal Headers
- Connecting to the Audio System
- Connecting Chassis Fan and Power Supply Cables
- Setting the BIOS Configuration Jumper
- Clearing Passwords
- Replacing the Battery
- 3 Updating the BIOS
- A Error Messages and Indicators
- B Regulatory Compliance

Intel Desktop Board DH57JG Product Guide
70
Lead-free 2LI/Pb-free 2LI Board
The electronics industry is transitioning to European Union (EU) Restriction of
Hazardous Substances (RoHS)-compliant products. The RoHS legislation restricts the
use of six materials. One of these restricted materials is lead. Lead is the most
common and problematic of the RoHS restricted materials.
There are exemptions in RoHS that allow the use of lead in some very limited locations
in electronic products. Maximum lead concentration values have been established for
RoHS-compliant electronic products that allow up to 1000 ppm of lead.
Lead-free/Pb-free is a nickname that is often used (or misused) for RoHS-compliant
products. In this case, the term "Lead-free/Pb-free" means that lead has been
removed where required by the RoHS legislation but still may exist as an impurity
below 1000 ppm.
The term "Lead-free 2LI/Pb-free 2LI" means lead-free second level interconnect (2LI).
The balls, leads, or pads used to connect the component to a printed circuit board are
lead-free, but the first level interconnect (FLI) is not lead-free. The use of lead in the
FLI is acceptable because of the RoHS "flip chip" or "die bump" interconnect
exemption.
Intel Desktop Board DH57JG is a lead-free second level interconnect product.
Table 20 shows the lead-free second level interconnect
marks as they appear on the
board and accompanying collateral. These marks are based on JEDEC standard
J-STD-609, “Marking and Labeling of Components, PCBs and PCBAs to Identify Lead,
Lead Free and Other Attributes.”
For more information concerning Intel’s lead-free initiatives, refer to:
http://www.intel.com/technology/silicon/leadfree.htm
.