Datasheet

Intel® Server Board S2600CW Family TPS Intel® Server Board S2600CW Platform Management

Revision1.11

The sensor is rearmed on power-on (AC or DC power-on transitions). It is not rearmed on

system resets in order to avoid multiple SEL events that could occur due to a potential reset

loop if the CATERR keeps recurring, which would be the case if the CATERR was due to an

MSID mismatch condition.

When the BMC detects that this aggregate CATERR signal has asserted, it can then go through

PECI to query each CPU to determine which one was the source of the error and write an OEM

code identifying the CPU slot into an event data byte in the SEL entry. If PECI is non-functional

(it isn’t guaranteed in this situation), then the OEM code should indicate that the source is

unknown.

Event data byte 2 and byte 3 for CATERR sensor SEL events

ED1 – 0xA1

ED2 – CATERR type

0: Unknown

1: CATERR

2: CPU Core Error (not supported on Intel® Server Systems supporting the Intel® Xeon®

processor E5-2600 v3 product family)

3: MSID Mismatch

4: CATERR due to CPU 3-strike timeout

ED3 – CPU bitmap that causes the system CATERR

[0]: CPU1

[1]: CPU2

[2]: CPU3

[3]: CPU4

When a CATERR Timeout event is determined to be a CPU 3-strike timeout, the BMC shall log

the logical FRU information (e.g. bus/dev/func for a PCIe device, CPU, or DIMM) that identifies

the FRU that caused the error in the extended SEL data bytes. In this case, Ext-ED0 will be set

to 0x70 and the remaining ED1-ED7 will be set according to the device type and info available.

5.3.11.5 MSID Mismatch Sensor

The BMC supports an MSID Mismatch sensor for monitoring for the fault condition that will

occur if there is a power rating incompatibility between a baseboard and a processor.

The sensor is rearmed on power-on (AC or DC power-on transitions).

5.3.12 Voltage Monitoring

The BMC provides voltage monitoring capability for voltage sources on the main board and

processors so that all major areas of the system are covered. This monitoring capability is

instantiated in the form of IPMI analog/threshold sensors.