Datasheet

Intel® Server Board S2600CW Family TPS Intel® Server Board S2600CW Functional Architecture
Revision1.11
25
- Multi-rank level memory sparing
- Failed DIMM isolation
3.3.1 Supported Memory
Table 3. RDIMM Support
Ranks Per DIMM
and Data Width
Memory Capacity
Per DIMM
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)
1DPC 2DPC
1.2V 1.2V
SRx4 8GB 2133 1866
SRx8 4GB 2133 1866
DRx8 8GB 2133 1866
DRx4 16GB 2133 1866
Table 4. LRDIMM Support
Ranks Per DIMM
and Data Width
Memory Capacity Per
DIMM
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)
1DPC 2DPC
1.2V 1.2V
QRx4 32GB 2133 2133
3.3.2 Memory Population Rules
 Each installed processor provides four channels of memory. On the Intel
®
Server Board
S2600CW each memory channel supports two memory slots, for a total possible 16
DIMMs installed.
 System memory is organized into physical slots on DDR4 memory channels that
belong to processor sockets.
 The memory channels from processor socket 1 are identified as Channel A, B, C and D.
The memory channels from processor socket 2 are identified as Channel E, F, G and H.
 Each memory slot on the server board is identified by channel, and slot number within
that channel. For example, DIMM_A1 is the first slot on Channel A on processor 1;
DIMM_E1 is the first DIMM socket on Channel E on processor 2.
 The memory slots associated with a given processor are unavailable if the
corresponding processor socket is not populated.
 A processor may be installed without populating the associated memory slots
provided a second processor is installed with associated memory. In this case, the
memory is shared by the processors. However, the platform suffers performance
degradation and latency due to the remote memory.