Datasheet

Intel® Server Board S2600CW Functional Architecture Intel® Server Board S2600CW Family TPS
24 Revision1.11
3.2.13 Trusted Platform Module (TPM)
Trusted Platform Module is bound to the platform and connected to the PCH via the LPC bus
or SPI bus. The TPM provides the hardware-based mechanism to store or “seal” keys and
other data to the platform. It also provides the hardware mechanism to report platform
attestations.
3.3 Integrated Memory Controller (IMC) and Memory Subsystem
This section describes the architecture that drives the memory subsystem, supported memory
types, memory population rules, and supported memory RAS features.
Figure 14. Memory Subsystem for Intel
®
Server Board S2600CW
Each installed processor includes an integrated memory controller (IMC). Each processor
supports 4 memory channels capable of supporting up to 2 DIMMs per channel. The
processor IMC supports the following:
 DDR4 ECC RDIMM
 DDR4 ECC LRDIMM
 Support for 4 Gb and 8 Gb DRAM Technologies
 Max Ranks per DDR channel – DDR4 LRDIMM: 16 (SR, DR, QR, 8R)
 Max Ranks per DDR channel – DDR4 RDIMM: 4 (SR, DR)
 IMCs can operate in either Independent mode (Maximum Performance mode) or
Lockstep mode (RASM)
 Memory RASM support:
- DRAM Single Device Data Correction (SDDC)
- Memory Disable and Map out for FRB
- Data scrambling with command and address
- DDR4 Command/Address parity check and retry
- Intra-socket memory mirroring
- Memory demand and patrol scrubbing
- HA and IMC corrupt data containment
- Rank level memory sparing