Datasheet

Functional Architecture Intel
®
Server Board S2400GP TPS
Revision 1.01
Intel order number G50295-002
40
3.8.16 Manageability
The chipset integrates several functions designed to manage the system and lower the total
cost of ownership (TCO) of the system. These system management functions are designed to
report errors, diagnose the system, and recover from system lockups without the aid of an
external microcontroller.
 TCO Timer. The chipset’s integrated programmable TCO timer is used to detect system
locks. The first expiration of the timer generates an SMI# that the system can use to
recover from a software lock. The second expiration of the timer causes a system reset
to recover from a hardware lock.
 Processor Present Indicator. The chipset looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the chipset will
reboot the system.
 ECC Error Reporting. When detecting an ECC error, the host controller has the ability
to send one of several messages to the chipset. The host controller can instruct the
chipset to generate SMI#, NMI, SERR#, or TCO interrupt.
 Function Disable. The chipset provides the ability to disable the following integrated
functions: LAN, USB, LPC, SATA, PCI Express* or SMBus*. Once disabled, these
functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts
or power management events are generated from the disabled functions.
 Intruder Detect. The chipset provides an input signal (INTRUDER#) that can be attached
to a switch that is activated by the system case being opened. The chipset can be
programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal.
3.8.17 System Management Bus (SMBus* 2.0)
The C600 chipset contains a SMBus* Host interface that allows the processor to communicate
with SMBus* slaves. This interface is compatible with most I2C devices. Special I2C commands
are implemented. The C600 chipset’s SMBus* host controller provides a mechanism for the
processor to initiate communications with SMBus* peripherals (slaves). Also, the C600 chipset
supports slave functionality, including the Host Notify protocol. Hence, the host controller
supports eight command protocols of the SMBus* interface (see System Management Bus
(SMBus*) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
The C600 chipset’s SMBus* also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all
SMBus* devices.
3.8.18 Intel
®
Active Management Technology (Intel
®
AMT)
Intel
®
Active Management Technology (Intel
®
AMT) is the next generation of client
manageability using the wired network. Intel
®
AMT is a set of advanced manageability features
developed as a direct result of IT customer feedback gained through Intel
®
market research.
With the new implementation of System Defense in C600 chipset, the advanced manageability
feature set of Intel
®
AMT is further enhanced.