Datasheet

Intel

Server Board S2400GP TPS Functional Architecture

Revision 1.01

Intel order number G50295-002

logged to SEL to alert the user that there is memory hardware that has failed and needs to be

replaced.

In Mirrored Channel Mode, the memory contents are mirrored between Channel B and Channel

C and also between Channel E and Channel F. As a result of the mirroring, the total physical

memory available to the system is half of what is populated. Mirrored Channel Mode requires

that Channel B and Channel C, and Channel E and Channel F must be populated identically with

regards to size and organization. DIMM slot populations within a channel do not have to be

identical but the same DIMM slot location across Channel B and Channel C and across Channel

E and Channel F must be populated the same.

3.6.4.4 Lockstep Channel Mode

In lockstep channel mode the cache-line is split across channels. This is done to support Single

Device Data Correction (SDDC) for DRAM devices with 8-bit wide data ports. Also, the same

address is used on both channels, such that an address error on any channel is detectable by

bad ECC. The iMC module always accumulates 32-bytes before forwarding data so there is no

latency benefit for disabling ECC.

Lockstep channels must be populated identically. That is, each DIMM in one channel must have

a corresponding DIMM of identical organization (number ranks, number banks, number rows,

number columns). DIMMs may be of different speed grades, but the iMC module will be

configured to operate all DIMMs according to the slowest parameters present by the Memory

Reference Code (MRC).

Performance in lockstep mode cannot be as high as with independent channels. The burst

length for DDR3 DIMMs is eight which is shared between two channels that are in lockstep

mode. Each channel of the pair provides 32 bytes to produce the 64-byte cache-line. DRAMs on

independent channels are configured to deliver a burst length of eight. The maximum read

bandwidth for a given Rank is half of peak. There is another

draw back in using lockstep mode, that is, higher power consumption since the total activation

power is about twice of the independent channel operation if comparing to same type of DIMMs.

In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel B

and Channel C, and Channel E and Channel F. Lockstep Channel mode is the only RAS mode

that allows SDDC for x8 devices. Lockstep Channel Mode requires that Channel B and Channel

C, and Channel E and Channel F must be populated identically with regards to size and

organization. DIMM slot populations within a channel do not have to be identical but the same

DIMM slot location across Channel B and Channel C and across Channel E and Channel F must

be populated the same.

3.6.4.5 Single Device Data Correction (SDDC)

SDDC – Single Device Data Correction is a technique by which data can be replaced by the

IMC from an entire x4 DRAM device which is failing, using a combination of CRC plus parity.

This is an automatic IMC driven hardware. It can be extended to x8 DRAM technology by

placing the system in Channel Lockstep Mode.

3.6.4.6 Error Correction Code (ECC) Memory

ECC uses “extra bits” – 64-bit data in a 72-bit DRAM array – to add an 8-bit calculated

“Hamming Code” to each 64 bits of data. This additional encoding enables the memory