Datasheet

Intel
®
Server Board S2400GP TPS Functional Architecture
Revision 1.01
Intel order number G50295-002
29
 BIOS flash
3.6.4 RAS Features
The server board supports the following memory RAS modes:
 Independent Channel Mode
 Rank Sparing Mode
 Mirrored Channel Mode
 Lockstep Channel Mode
 Single Device Data Correction (SDDC)
 Error Correction Code (ECC) Memory
 Demand Scrubbing for ECC Memory
 Patrol Scrubbing for ECC Memory
Regardless of RAS mode, the requirements for populating within a channel given in the section
3.6.2 must be met at all times. Note that support of RAS modes that require matching DIMM
population between channels (Mirrored and Lockstep) require that ECC DIMMs be populated.
Independent Channel Mode is the only mode that supports non-ECC DIMMs in addition to
ECC DIMMs.
For RAS modes that require matching populations, the same slot positions across channels
must hold the same DIMM type with regards to size and organization. DIMM timings do not
have to match but timings will be set to support all DIMMs populated (that is, DIMMs with slower
timings will force faster DIMMs to the slower common timing modes).
3.6.4.1 Independent Channel Mode
In non-ECC and x4 SDDC configurations, each channel is running independently (nonlock-step),
that is, each cache-line from memory is provided by a channel. To deliver the 64-byte cache-line
of data, each channel is bursting eight 8-byte chunks. Back to back data transfer in the same
direction and within the same rank can be sent back-to-back without any dead-cycle. The
independent channel mode is the recommended method to deliver most efficient power and
bandwidth as long as the x8 SDDC is not required.
3.6.4.2 Rank Sparing Mode
In Rank Sparing Mode, one rank is a spare of the other ranks on the same channel. The spare
rank is held in reserve and is not available as system memory. The spare rank must have
identical or larger memory capacity than all the other ranks (sparing source ranks) on the same
channel. After sparing, the sparing source rank will be lost.
Rank Sparing Mode enhances the system’s RAS capability by “swapping out” failing ranks of
DIMMs. Rank Sparing is strictly channel and rank oriented. Each memory channel is a
Sparing Domain.
For Rank Sparing to be available as a RAS option, there must be 2 or more single rank or dual
rank DIMMs, or at least one quad rank DIMM installed on each memory channel.
Rank Sparing Mode is enabled or disabled in the Memory RAS and Performance Configuration
screen in the <F2> Bios Setup Utility.