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Intel

Server Board S2400GP

Technical Product Specification

Intel order number G50295-002

Revision 1.01

May, 2012

Enterprise Platforms and Services Division - Marketing

Summary of content (156 pages)

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Intel®Server Board S2400GP Technical Product Specification Intel order number G50295-002 Revision 1.
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Revision History Intel®Server Board S2400GP (Preliminary) TPS Revision History Date May 2012 Revision Number 1.0 Modifications Initial release. May 2012 1.01 Add NIC Port MAC address. Disclaimers ® Information in this document is provided in connection with Intel products. No license, express or implied, by ® estoppel or otherwise, to any intellectual property rights is granted by this document.
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Intel®Server Board S2400GP TPS Table of Contents Table of Contents 1. Introduction ........................................................................................................................ 1 1.1 Chapter Outline ...................................................................................................... 1 1.2 Server Board Use Disclaimer ................................................................................. 1 2. Overview ...................................................
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Table of Contents Intel®Server Board S2400GP TPS 3.8.17 System Management Bus (SMBus* 2.0) .............................................................. 40 3.8.18 Intel® Active Management Technology (Intel® AMT) ............................................. 40 3.8.19 Integrated NVSRAM Controller ............................................................................ 41 3.8.20 Intel® Virtualization Technology for Direct I/O (Intel® VT-d) ................................... 41 3.8.
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Intel®Server Board S2400GP TPS Table of Contents 6.7 Fault Resilient Booting (FRB) ............................................................................... 65 6.8 Sensor Monitoring ................................................................................................ 65 6.9 Field Replaceable Unit (FRU) Inventory Device ................................................... 66 6.10 System Event Log (SEL) ......................................................................................
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Table of Contents Intel®Server Board S2400GP TPS 8.3 System Management Headers ............................................................................. 95 8.3.1 Intel® Remote Management Module 4 Connector ................................................. 95 8.3.2 TPM connector ..................................................................................................... 96 8.3.3 LCP Header .........................................................................................................
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Intel®Server Board S2400GP TPS List of Figures List of Figures Figure 1. Intel® Server Board S2400GP Layout (S2400GP4 as example) ................................... 4 Figure 2. Intel® Server Board S2400GP Components ................................................................. 5 Figure 3. Major Board Components ............................................................................................ 7 Figure 4. Intel® Server Board S2400GP – Mounting Hole Locations (1 of 2) ........................
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List of Tables Intel®Server Board S2400GP TPS List of Tables Table 1. Intel® Server Boards S2400GP Feature Set .................................................................. 2 Table 2. Intel® Server Boards S2400GP Components ................................................................. 6 Table 3. Mixed Processor Configurations .................................................................................. 19 Table 4. UDIMM Support Guidelines .....................................................
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Intel®Server Board S2400GP TPS List of Tables Table 41. Pin-out of Internal Low-Profile USB Connector for Solid State Drive ....................... 100 Table 42. Internal Type A USB Port Pin-out ............................................................................ 101 Table 43. SSI 4-pin Fan Header Pin-out ................................................................................. 101 Table 44. SSI 6-pin Fan Header Pin-out ......................................................................
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List of Tables Intel®Server Board S2400GP TPS x Revision 1.
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Intel®Server Board S2400GP TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of the Intel® Server Board S2400GP. In addition, you can obtain design-level information for specific subsystems by ordering the External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem.
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Overview 2. Intel®Server Board S2400GP TPS Overview The Intel® Server Board S2400GP is monolithic printed circuit boards (PCBs) with features designed to support the pedestal and rack server markets. 2.1 Intel®Server Boards S2400GP Feature Set ® Table 1. Intel Server Boards S2400GP Feature Set Feature Processors    Memory         Description ® ® Support for one or two Intel Xeon E5-2400 series Processor(s) in an FC-LGA 1356 Socket B2 package with Thermal Design Power up to 95W ® ® 6.
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Intel®Server Board S2400GP TPS Overview Feature I/O control support Description External connections:  DB9 serial port A connection  Two RJ-45 NIC connectors for 10/100/1000 Mb connections: Dual GbE through the ® Intel Ethernet Controller I350 (for S2400GP2 Sku)  Four RJ-45 NIC connectors for 10/100/1000 Mb connections: Dual GbE through the ® Intel Ethernet Controller I350 (for S2400GP4 sku)  Four USB 2.
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Overview 2.2 Intel®Server Board S2400GP TPS Server Board Layout ® Figure 1. Intel Server Board S2400GP Layout (S2400GP4 as example) 2.3 Server Board Connector and Component Layout The following figure shows the layout of the server board. Each connector and major component is identified by a number or letter, and a description is given below the figure. 4 Revision 1.
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Intel®Server Board S2400GP TPS Overview ® Figure 2. Intel Server Board S2400GP Components 5 Revision 1.
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Overview Intel®Server Board S2400GP TPS ® Table 2.
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Intel®Server Board S2400GP TPS 2.4 Overview Server Board Mechanical Drawings Figure 3. Major Board Components 7 Revision 1.
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Overview Intel®Server Board S2400GP TPS ® Figure 4. Intel Server Board S2400GP – Mounting Hole Locations (1 of 2) 8 Revision 1.
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Intel®Server Board S2400GP TPS Overview ® Figure 5. Intel Server Board S2400GP – Mounting Hole Locations (2 of 2) 9 Revision 1.
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Overview Intel®Server Board S2400GP TPS ® Figure 6. Intel Server Boards S2400GP – Major Connector Pin-1 Locations (1 of 3) 10 Revision 1.
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Intel®Server Board S2400GP TPS Overview ® Figure 7. Intel Server Boards S2400GP – Major Connector Pin-1 Locations (2 of 3) 11 Revision 1.
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Overview Intel®Server Board S2400GP TPS ® Figure 8. Intel Server Boards S2400GP – Major Connector Pin-1 Locations (2 of 3) 12 Revision 1.
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Intel®Server Board S2400GP TPS Overview ® Figure 9. Intel Server Boards S2400GP – Primary Side Keep-out Zone 13 Revision 1.
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Overview Intel®Server Board S2400GP TPS ® Figure 10. Intel Server Boards S2400GP – Primary Side Card Side Keep-out Zone 14 Revision 1.
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Intel®Server Board S2400GP TPS Overview ® Figure 11. Intel Server Boards S2400GP – Second Side Keep-out Zone 2.5 Server Board Rear I/O Layout The following drawing shows the layout of the rear I/O components for the server boards. 15 Revision 1.
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Overview Intel®Server Board S2400GP TPS A Serial Port A E NIC Port 3 (top), 4 (bottom) for S2400GP4 sku only B Video F Diagnostic LEDs C NIC Port 1 (1 Gb) Management Port USB_0(top), 1(bottom) G ID LED D NIC Port 2 _USB Port 2 (top), 3 (bottom) H System Status LED ® Figure 12. Intel Server Boards S2400GP Rear I/O Layout 16 Revision 1.
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Intel®Server Board S2400GP TPS 3. Functional Architecture Functional Architecture The architecture and design of the Intel® Server Board S2400GP is based on the Intel® C600 chipset. The chipset is designed for systems based on the Intel® Xeon® processor in an FC-LGA 1356 Socket B2 package with Intel® QuickPath Interconnect (Intel® QPI). This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up the server boards.
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Functional Architecture Intel®Server Board S2400GP TPS Visit the Intel web site for a complete list of supported processors. 3.2 Processor Socket Assembly Each processor socket of the server board is pre-assembled with an Independent Latching Mechanism (ILM) and Back Plate which allow for secure placement of the processor and processor heat to the server board. The illustration below identifies each sub-assembly component. Figure 14. Processor Socket Assembly 3.
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Intel®Server Board S2400GP TPS      Functional Architecture Both processors must have the same number of cores. Both processors must have the same cache size for all levels of processor cache memory. Processors with different speeds can be mixed in a system, given the prior rules are met. If this condition is detected, all processor speeds are set to the lowest common denominator (highest common speed) and an error is reported.
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Functional Architecture Intel®Server Board S2400GP TPS Error Processor cores/threads not identical Severity Fatal System Action The BIOS detects the error condition and responds as follows: Logs the POST Error Code into the SEL. Alerts the BMC to set the System Status LED to steady Amber. Displays “0191: Processor core/thread count mismatch detected” message in the Error Manager. Takes Fatal Error action (see above) and will not boot until the fault condition is remedied.
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Intel®Server Board S2400GP TPS Error Processor microcode update failed Functional Architecture Severity Major System Action The BIOS detects the error condition and responds as follows: Logs the POST Error Code into the SEL. Displays “816x: Processor 0x unable to apply microcode update” message in the Error Manager or on the screen. Takes Major Error action.
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Functional Architecture 3.4 Intel®Server Board S2400GP TPS Processor Function Overview With the release of the Intel® Xeon® processor E5-2400 product family, several key system components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module (IIO), have been combined into a single processor package and feature per socket; One Intel® QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 24 lanes of Gen 3 PCI Express* links capable of 8.
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Intel®Server Board S2400GP TPS 3.5 Functional Architecture Intel®QuickPath Interconnect The Intel® QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used in the processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency.
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Functional Architecture Intel®Server Board S2400GP TPS  Command launch modes of 1n/2n  RAS Support: o Rank Level Sparing and Device Tagging o Demand and Patrol Scrubbing o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device. Independent channel mode supports x4 SDDC.
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Intel®Server Board S2400GP TPS Functional Architecture Supported and Validated Supported but not Validated Table 5. RDIMM Support Guidelines Ranks Per DIMM and Data Width Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per Channel (DPC)2,3,4 1 Slot per Channel 2 Slots per Channel Memory Capacity Per DIMM1 1DPC 1.35V 1DPC 1.5V 1066 1333 1600 1.35V 2DPC 1.5V 1066 1333 1600 1.35V 1.
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Functional Architecture Intel®Server Board S2400GP TPS Notes: 1. Physical Rank is used to calculate DIMM Capacity. 2. Supported and validated DRAM Densities are 2Gb and 4Gb. 3. Command Address Timing is 1N. 4. The speeds are estimated targets and will be verified through simulation. 5. For Memory Population Rules, please refer to the Romley Platform Design Guide. 6. DDP - Dual Die Package DRAM stacking. P – Planer monolithic DRAM Die. Supported and Validated Supported but not Validated 3.6.
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Intel®Server Board S2400GP TPS A1 A2 Functional Architecture Processor Socket 1 B1 B2 C1 C2 D1 D2 Processor Socket 2 E1 E2 F1 F2 ® Figure 15. Intel Server Board S2400GP DIMM Slot Layout The following are generic DIMM population requirements that generally apply to the Intel® Server Board S2400GP.  All DIMMs must be DDR3 DIMMs  Registered DIMMs must be ECC only; Unbuffered DIMMs can be ECC or non-ECC. However, Intel® only validates and supports ECC memory for its server products.
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Functional Architecture Intel®Server Board S2400GP TPS  Mixing of DDR3 voltages is not validated within a socket or across sockets by Intel®. If 1.35V (DDR3L) and 1.50V (DDR3) DIMMs are mixed, the DIMMs will run at 1.50V.  Mixing of DDR3 operating frequencies is not validated within a socket or across sockets by Intel®. If DIMMs with different frequencies are mixed, all DIMMs will run at the common lowest frequency.  A maximum of eight logical ranks (ranks seen by the host) per channel is allowed.
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Intel®Server Board S2400GP TPS  Functional Architecture BIOS flash 3.6.4 RAS Features The server board supports the following memory RAS modes:  Independent Channel Mode  Rank Sparing Mode  Mirrored Channel Mode  Lockstep Channel Mode  Single Device Data Correction (SDDC)  Error Correction Code (ECC) Memory  Demand Scrubbing for ECC Memory  Patrol Scrubbing for ECC Memory Regardless of RAS mode, the requirements for populating within a channel given in the section 3.6.
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Functional Architecture Intel®Server Board S2400GP TPS When Sparing Mode is operational, for each channel, the largest size memory rank is reserved as a “spare” and is not used during normal operations. The impact on Effective Memory Size is to subtract the sum of the reserved ranks from the total amount of installed memory. Hardware registers count the number of Correctable ECC Errors for each rank of memory on each channel during operations and compare the count against a Correctable Error Threshold.
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Intel®Server Board S2400GP TPS Functional Architecture logged to SEL to alert the user that there is memory hardware that has failed and needs to be replaced. In Mirrored Channel Mode, the memory contents are mirrored between Channel B and Channel C and also between Channel E and Channel F. As a result of the mirroring, the total physical memory available to the system is half of what is populated.
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Functional Architecture Intel®Server Board S2400GP TPS controller to detect and report single or multiple bit errors when data is read, and to correct single-bit errors. 3.1.1.1.1 Correctable Memory ECC Error Handling A “Correctable ECC Error” is one in which a single-bit error in memory contents is detected and corrected by use of the ECC Hamming Code included in the memory data. For a correctable error, data integrity is preserved, but it may be a warning sign of a true failure to come.
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Intel®Server Board S2400GP TPS 3.7 Functional Architecture Processor Integrated I/O Module (IIO) The processor’s integrated I/O module provides features traditionally supported through chipset components. The integrated I/O module provides the following features:  PCI Express* Interfaces: The integrated I/O module incorporates the PCI Express* interface and supports up to 24 lanes of PCI Express*.
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Functional Architecture Intel®Server Board S2400GP TPS Figure 16. Functional Block Diagram of Processor IIO Sub-system The following sub-sections will describe the server board features that are directly supported by the processor IIO module. These include the Riser Card Slots, Network Interface, and connectors for the optional I/O modules and SAS Module. Features and functions of the Intel® C600 Series chipset will be described in its own dedicated section. 3.7.
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Intel®Server Board S2400GP TPS Functional Architecture Table 8. External RJ45 NIC Port LED Definition LED Color Green/Amber (Right) Green (Left) LED State NIC State Off 10 Mbps Amber 100 Mbps Green 1000 Mbps On Active Connection Blinking Transmit/Receive activity The server board has seven MAC addresses programmed at the factory for S2400GP4.
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Functional Architecture Intel®Server Board S2400GP TPS list in Chapter 1. Figure 17.
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Intel®Server Board S2400GP TPS Functional Architecture  Integrated NVSRAM controller  Virtualization Technology for Direct I/O (Intel® VT-d)  JTAG Boundary-Scan  KVM/Serial Over LAN (SOL) Function 3.8.1 Digital Media Interface (DMI) Digital Media Interface (DMI) is the chip-to-chip connection between the processor and C600 chipset. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities.
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Functional Architecture Intel®Server Board S2400GP TPS 3.8.6 PCI Interface The C600 chipset PCI interface provides a 33 MHz, Revision 2.3 implementation. The C600 chipset integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal C600 chipset requests. This allows for combinations of up to four PCI down devices and PCI slots. 3.8.7 Low Pin Count (LPC) Interface The C600 chipset implements an LPC Interface as described in the LPC 1.1 Specification.
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Intel®Server Board S2400GP TPS Functional Architecture 3.8.11 Universal Serial Bus (USB) Controller The C600 chipset has up to two Enhanced Host Controller Interface (EHCI) host controllers that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The C600 chipset supports up to fourteen USB 2.0 ports. All fourteen ports are high-speed, full-speed, and low-speed capable. 3.8.
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Functional Architecture Intel®Server Board S2400GP TPS 3.8.16 Manageability The chipset integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.  TCO Timer. The chipset’s integrated programmable TCO timer is used to detect system locks.
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Intel®Server Board S2400GP TPS Functional Architecture 3.8.19 Integrated NVSRAM Controller The C600 chipset has an integrated NVSRAM controller that supports up to 32KB external device. The host processor can read and write data to the NVSRAM component. 3.8.20 Intel®Virtualization Technology for Direct I/O (Intel®VT-d) The C600 chipset provides hardware support for implementation of Intel® Virtualization Technology with Directed I/O (Intel® VT-d).
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Functional Architecture  Intel®Server Board S2400GP TPS Intel® Rapid Storage Technology (RSTe) supporting SATA RAID levels 0,1,5,10 The server board is capable of supporting additional chipset embedded SAS and RAID options from the SCU controller when configured with one of several available Intel® RAID C600 Upgrade Keys. Upgrade keys install onto a 4-pin connector on the server board labeled “STOR_UPG_KEY”. The following table identifies available upgrade key options and their supported features.
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Intel®Server Board S2400GP TPS Functional Architecture 3.8.
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Functional Architecture Intel®Server Board S2400GP TPS Figure 18. Integrated Baseboard Management Controller (BMC) Overview 44 Revision 1.
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Intel®Server Board S2400GP TPS Functional Architecture Figure 19. Integrated BMC Hardware 3.
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Functional Architecture Intel®Server Board S2400GP TPS 2D Mode 2D Video Mode Support 1152x864 8 bpp X 16 bpp X 24 bpp X 32 bpp X 1280x1024 X X X X 1600x1200** X X ** Video resolutions at 1600x1200 are only supported through the external video connector located on the rear I/O section of the server board. Utilizing the optional front panel video connector may result in lower video resolutions. The server board provides two video interfaces.
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Intel®Server Board S2400GP TPS Functional Architecture  Eight I2C interfaces with master-slave and SMBus timeout support. All interfaces are SMBus 2.0 compliant.
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Functional Architecture  IP Address: Static.  All users disabled. Intel®Server Board S2400GP TPS 48 Revision 1.
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Intel®Server Board S2400GP TPS System Security 4 System Security 4.1 BIOS Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress automatic USB device reordering. There is also an option to require a Power On password entry in order to boot the system.
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System Security Intel®Server Board S2400GP TPS In addition to restricting access to most Setup fields to viewing only when a User password is entered, defining a User password imposes restrictions on booting the system. In order to simply boot in the defined boot order, no password is required. However, the F6 Boot popup prompts for a password, and can only be used with the Administrator password.
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Intel®Server Board S2400GP TPS     System Security Produces EFI and legacy interfaces to a TPM-enabled operating system for using TPM. Produces ACPI TPM device and methods to allow a TPM-enabled operating system to send TPM administrative command requests to the BIOS. Verifies operator physical presence. Confirms and executes operating system TPM administrative command requests. Provides BIOS Setup options to change TPM security states and to clear TPM ownership.
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System Security Intel®Server Board S2400GP TPS 4.3.3 Security Screen To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel® logo displays. The following message displays on the diagnostics screen and under the Quiet Boot logo screen: Press to enter setup When the Setup is entered, the Main screen displays.
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Intel®Server Board S2400GP TPS System Security Table 12. TPM Setup Utility – Security Configuration Screen Fields Setup Item TPM State* Options Enabled and Activated Help Text Enabled and Deactivated Comments Information only. Shows the current TPM device state. Disabled and Activated A disabled TPM device will not execute commands that use TPM functions and TPM security operations will not be available.
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System Security Intel®Server Board S2400GP TPS Technology enabled (both VT-x and VT-d), an Intel® Trusted Execution Technology-enabled processor, chipset and BIOS, Authenticated Code Modules, and an Intel® Trusted Execution Technology compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel® Trusted Execution Technology requires the system to include a TPM v1.
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Intel®Server Board S2400GP TPS Technology Support 5 Technology Support 5.1 Intel®Trusted Execution Technology The Intel® Xeon® Processor E5 4600/2600/2400/1600 Product Families support Intel® Trusted Execution Technology (Intel® TXT), which is a robust security environment designed to help protect against software-based attacks. Intel® Trusted Execution Technology integrates new security features and capabilities into the processor, chipset and other platform components.
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Technology Support Intel®Server Board S2400GP TPS For more information on the DMAR table and the DRHD entry format, refer to the Intel® Virtualization Technology for Directed I/O Architecture Specification. For more general information about VT-x, VT-d, and VT-c, a good reference is Enabling Intel® Virtualization Technology Features and Benefits White Paper. 5.
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Intel®Server Board S2400GP TPS Technology Support code used by OS-Directed Power Management (OSPM) for negotiating processor P and T state changes for power limiting. PMBus*-compliant power supplies provide the capability to monitoring input power consumption, which is necessary to support NM. Below are the some of the applications of Intel® Intelligent Power Node Manager technology.
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Platform Management Functional Overview 6 Intel®Server Board S2400GP TPS Platform Management Functional Overview Platform management functionality is supported by several hardware and software components integrated on the server board that work together to control system functions, monitor and report system health, and control various thermal and performance features in order to maintain (when possible) server functionality in the event of component failure and/or environmentally stressed conditions.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview See also the Intelligent Platform Management Interface Specification Second Generation v2.0. 6.1.2 Non IPMI Features The BMC supports the following non-IPMI features.   In-circuit BMC firmware update BMC FW reliability enhancements: o Redundant BMC boot blocks to avoid possibility of a corrupted boot block resulting in a scenario that prevents a user from updating the BMC.
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Platform Management Functional Overview                   Intel®Server Board S2400GP TPS Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs). Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs). E-mail alerting Embedded web server o Support for embedded web server UI in Basic Manageability feature set.
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Intel®Server Board S2400GP TPS     Platform Management Functional Overview Enhancements to fan speed control. DCMI 1.1 compliance (product-specific). Support for embedded web server UI in Basic Manageability feature set.
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Platform Management Functional Overview Feature Hot-Swap Fan Support X X Acoustic Management X X Diagnostic Beep Code Support X X Power State Retention X X ARP/DHCP Support X X PECI Thermal Management Support X X E-mail Alerting X X Embedded Web Server X X SSH Support X X Basic Advanced Integrated KVM X Integrated Remote Media Redirection X Lightweight Directory Access Protocol (LDAP) X X Intel Intelligent Power Node Manager Support X X SMASH CLP X X ® 6.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview  Interrupt controller  Multiple Serial Peripheral Interface (SPI) flash interfaces  NAND/Memory interface  Sixteen mailbox registers for communication between the BMC and host  LPC ROM interface  BMC watchdog timer capability  SD/MMC card controller with DMA support  LED support with programmable blink rate controls on GPIOs  Port 80h snooping capability  Secondary Service Processor (SSP), which provides th
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Platform Management Functional Overview 6.5 Intel®Server Board S2400GP TPS Power Control Sources The server board supports several power control sources which can initiate a power-up or power-down activity. Table 16.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview 1. Timeout value for the rotation period can be set using this parameter. Potentially, there will be incorrect ACPI Power State reported by the BMC. 2. Reversion of temporary test modes for the BMC back to normal operational modes. 3. FP status LED and DIMM fault LEDs may not reflect BIOS detected errors. 6.
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Platform Management Functional Overview  Intel®Server Board S2400GP TPS Processor errors The information gathered from physical sensors is translated into IPMI sensors as part of the “IPMI Sensor Model”. The BMC also reports various system state changes by maintaining virtual sensors that are not specifically tied to physical hardware. See Appendix B – Integrated BMC Sensor Tables for additional sensor information. 6.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview System fan speeds are controlled through pulse width modulation (PWM) signals, which are driven separately for each domain by integrated PWM hardware. Fan speed is changed by adjusting the duty cycle, which is the percentage of time the signal is driven high in each pulse 6.11.
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Platform Management Functional Overview 6.11.6 Intel®Server Board S2400GP TPS Quiet Fan Idle Mode This feature can be [Enabled] or [Disabled]. If enabled, the fan will either stopped or shift to a lower speed when the aggregate sensor temperatures are satisfied indicating the system is at ideal thermal/light loading conditions. When the aggregate sensor temperatures not satisfied, the fan will shift back to normal control curves.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview 6.11.8 Thermal Sensor Input to Fan Speed Control The BMC uses various IPMI sensors as input to the fan speed control. Some of the sensors are IPMI models of actual physical sensors whereas some are “virtual” sensors whose values are derived from physical sensors using calculations and/or tabular information.
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Platform Management Functional Overview Intel®Server Board S2400GP TPS Figure 21. Fan Speed Control Process 6.11.9 Memory Thermal Throttling The server board provides support for system thermal management through open loop throttling (OLTT) and closed loop throttling (CLTT) of system memory. Normal system operation uses closed-loop thermal throttling (CLTT) and DIMM temperature monitoring as major factors in overall thermal and acoustics management.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview 6.
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Platform Management Functional Overview Intel®Server Board S2400GP TPS The BMC IPMB slave address is 20h. The BMC both sends and receives IPMB messages over the IPMB interface. Non-IPMB messages received by means of the IPMB interface are discarded. Messages sent by the BMC can either be originated by the BMC, such as initialization agent operation, or by another source. One example is KCS-IPMB bridging. 6.12.3 LAN Interface The BMC implements both the IPMI 1.5 and IPMI 2.0 messaging models.
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Intel®Server Board S2400GP TPS 6.12.3.2.2 Platform Management Functional Overview Dedicated Management Channel An additional LAN channel dedicated to BMC usage and not available to host SW is supported through an optional RMM4 add-in card. There is only a PHY device present on the RMM4 addin card. The BMC has a built-in MAC module that uses the RGMII interface to link with the card’s PHY. Therefore, for this dedicated management interface, the PHY and MAC are located in different devices.
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Platform Management Functional Overview  Intel®Server Board S2400GP TPS BMC LAN 3 (Dedicated NIC) ----- 100Mb 6.12.3.3 IPV6 Support In addition to IPv4, the server board has support for IPv6 for manageability channels. Configuration of IPv6 is provided by extensions to the IPMI Set and Get LAN Configuration Parameters commands as well as through a Web Console IPv6 configuration web page. The BMC supports IPv4 and IPv6 simultaneously so they are both configured separately and completely independently.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview functionality is configurable through IPMI methods as well as through the BMC’s Embedded UI, allowing for user to specify the physical LAN links constitute the redundant network paths or physical LAN links constitute different network paths. BMC will support only a all or nothing” approach – that is, all interfaces bonded together, or none are bonded together. The LAN Failover feature applies only to BMC LAN traffic.
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Platform Management Functional Overview 6.12.3.5.
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Intel®Server Board S2400GP TPS 6.12.3.5.
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Platform Management Functional Overview Intel®Server Board S2400GP TPS 6.12.4 Address Resolution Protocol (ARP) The BMC can receive and respond to ARP requests on BMC NICs. Gratuitous ARPs are supported, and disabled by default. 6.12.5 Internet Control Message Protocol (ICMP) The BMC supports the following ICMP message types targeting the BMC over integrated NICs:   Echo request (ping): The BMC sends an Echo Reply.
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Intel®Server Board S2400GP TPS  Platform Management Functional Overview If the BMC is configure for static (prior to disabling VLAN), when VLAN is disabled, the BMC has the same IP address that was configured before. It is left to the management application to configure a different IP address if that is not suitable for LAN. 6.12.7 Secure Shell (SSH) Secure Shell (SSH) connections are supported for SMASH-CLP sessions to the BMC. 6.12.8 Serial-over-LAN (SOL 2.0) The BMC supports IPMI 2.0 SOL. IPMI 2.
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Platform Management Functional Overview Intel®Server Board S2400GP TPS Additionally, the BMC supports the following PEF actions:  Power off  Power cycle  Reset  OEM action  Alerts The “Diagnostic interrupt” action is not supported. 6.12.10 LAN Alerting The BMC supports sending embedded LAN alerts, called SNMP PET (Platform Event traps), and SMTP email alerts. The BMC supports a minimum of four LAN alert destinations. 6.12.10.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview The SM-CLP utilized by a remote user by connecting a remote system through one of the system NICs. It is possible for third party management applications to create scripts using this CLP and execute them on server to retrieve information or perform management tasks such as reboot the server, configure events, and so on. The BMC embedded SM-CLP feature includes the following capabilities:  Power on/off/reset the server.
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Platform Management Functional Overview Intel®Server Board S2400GP TPS shall authenticate the user before allowing a web session to be initiated. Encryption using 128bit SSL is supported. User authentication is based on user id and password. The GUI presented by the embedded web server authenticates the user before allowing a web session to be initiated. It presents all functions to all users but grays-out those functions that the user does not have privilege to execute.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview  Display of ME sensor data. Only sensors that have associated SDRs loaded will be displayed.  Ability to save the SEL to a file.  Ability to force HTTPS connectivity for greater security. This is provided through a configuration option in the UI.  Display of processor and memory information as is available over IPMI over LAN.  Ability to get and set Node Manager (NM) power policies.
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Platform Management Functional Overview Intel®Server Board S2400GP TPS  There is no precedence or lock-out mechanism for the control sources. When a new request arrives, previous requests are terminated. For example, if the chassis ID button is pressed, then the chassis ID LED changes to solid on. If the button is pressed again, then the chassis ID LED turns off.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview  PCI configuration data for on-board devices and add-in cards. The first 256 bytes of PCI configuration data is captured for each device for each boot.  System memory map. The system memory map is provided by BIOS on the current boot. This includes the EFI memory map and the Legacy (E820) memory map depending on the current boot.  Power supplies debug capability.
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Platform Management Functional Overview Intel®Server Board S2400GP TPS Table 20.
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Intel®Server Board S2400GP TPS Platform Management Functional Overview configured for system management. The BMC uses a standard Open LDAP implementation for Linux*. Only open LDAP is supported by BMC. Windows* and Novel* LDAP are not supported. 87 Revision 1.
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Advanced Management Feature Support (RMM4) 7 Intel®Server Board S2400GP TPS Advanced Management Feature Support (RMM4) The integrated baseboard management controller has support for advanced management features which are enabled when an optional Intel® Remote Management Module 4 (RMM4) is installed. RMM4 is comprised of two boards – RMM4 lite and the optional Dedicated Server Management NIC (DMN). Table 22.
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Intel®Server Board S2400GP TPS Advanced Management Feature Support (RMM4) ® Figure 23. Intel RMM4 Dedicated Management NIC Installation If the optional Dedicated Server Management NIC is not used then the traffic can only go through the onboard Integrated BMC-shared NIC and will share network bandwidth with the host system. Advanced manageability features are supported over all NIC ports enabled for server manageability. 7.
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Advanced Management Feature Support (RMM4) Intel®Server Board S2400GP TPS Other attributes of this feature include:  Encryption of the redirected screen, keyboard, and mouse  Compression of the redirected screen.  Ability to select a mouse configuration based on the OS type.  supports user definable keyboard macros.
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Intel®Server Board S2400GP TPS Advanced Management Feature Support (RMM4) 7.1.3 Security The KVM redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual algorithm that is used is negotiated with the client based on the client’s capabilities. 7.1.4 Availability The remote KVM session is available even when the server is powered-off (in stand-by mode). No re-start of the remote KVM session shall be required during a server reset or power on/off.
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Advanced Management Feature Support (RMM4) Intel®Server Board S2400GP TPS  The media redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual algorithm that is used is negotiated with the client based on the client’s capabilities.  A remote media session is maintained even when the server is powered-off (in standby mode). No restart of the remote media session is required during a server reset or power on/off.
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Intel®Server Board S2400GP TPS On-board Connector/Header Overview 8 On-board Connector/Header Overview 8.1 Board Connector Information The following section provides detailed information regarding all connectors, headers, and jumpers on the server boards. The following table lists all connector types available on the board, as well as the corresponding preference designators printed on the silkscreen. Table 23.
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On-board Connector/Header Overview Intel®Server Board S2400GP TPS Connector Connector Type Pin Count Internal USB 2 Header 10 USB Solid State Drive 1 Header 9 Internal USB 1 Type-A USB 4 Chassis Intrusion 1 Header 2 Serial ATA 6 Header(white) 7 SAS 2 SFF8087 miniSAS 36 HSBP_I2C 1 Header 3 SATA SGPIO 1 Header 4 LCP 1 Header 7 IPMB 1 Header 4 Configuration jumpers TPM 8.
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Intel®Server Board S2400GP TPS On-board Connector/Header Overview Pin 1 2 3 4 5 6 7 8 Signal GND of Pin 5 GND of Pin 6 GND of Pin 7 GND of Pin 8 +12 Vdc CPU1 +12 Vdc CPU1 +12 Vdc DDR3_CPU1 +12 Vdc DDR3_CPU1 Color Black Black Black Black Yellow/black Yellow/black Yellow/black Yellow/black Table 26. Power Supply Auxiliary Signal Connector Pin-out Pin 1 2 3 4 5 8.3 Signal SMB_CLK_FP_PWR_R SMB_DAT_FP_PWR_R SMB_ALRT_3_ESB_R 3.3 V SENSE3.
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On-board Connector/Header Overview Intel®Server Board S2400GP TPS ® Table 28. Intel RMM4 – Lite Connector Pin-out 1 3 Pin Signal Name 3V3_AUX N/A 2 4 Pin SPI_RMM4_LITE_DI SPI_RMM4_LITE_CLK Signal Name 5 7 SPI_RMM4_LITE_DO SPI_RMM4_LITE_CS_N 6 8 GND GND 8.3.2 TPM connector Table 29.
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Intel®Server Board S2400GP TPS 8.4 On-board Connector/Header Overview Front Panel Connector The server board provides a 30-pin SSI front panel connector for use with Intel® and third-party chassis. The following table provides the pin-out for this connector: Table 33.
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On-board Connector/Header Overview Intel®Server Board S2400GP TPS Table 35. RJ-45 10/100/1000 NIC Connector Pin-out Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal Name GND P1V8_NIC NIC_A_MDI3P NIC_A_MDI3N NIC_A_MDI2P NIC_A_MDI2N NIC_A_MDI1P NIC_A_MDI1N NIC_A_MDI0P NIC_A_MDI0N NIC_LINKA_1000_N (LED NIC_LINKA_100_N (LED) NIC_ACT_LED_N NIC_LINK_LED_N GND GND 8.5.3 SATA Connectors The server board provides up to 6 SATA connectors: SATA-0 to SATA-5, and 2 MiniSAS connectors: SCU-0 and SCU-1.
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Intel®Server Board S2400GP TPS On-board Connector/Header Overview Signal Description GROUND GROUND GROUND GROUND Pin# MTH1 MTH2 MTH3 MTH4 Pin# MTH5 MTH6 MTH7 MTH8 Signal Description GROUND GROUND GROUND GROUND Signal Description GROUND SAS4_RX_C_DP SAS4_RX_C_DN GROUND SAS5_RX_C_DP SAS5_RX_C_DN GROUND TP_SAS2_BACKPLANE_TYPE GROUND SGPIO_SAS2_DATAOUT SGPIO_SAS2_DATAIN GROUND SAS6_RX_C_DP SAS6_RX_C_DN GROUND SAS7_RX_C_DP SAS7_RX_C_DN GROUND GROUND GROUND GROUND GROUND Pin# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
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On-board Connector/Header Overview Pin 7 8 9 Intel®Server Board S2400GP TPS Signal Name SPB_DTR SPB_RI GND Description DTR (Data terminal ready) RI (Ring indicate) Ground 8.5.5 USB Connector The following table details the pin-out of the external USB connectors found on the back edge of the server boards. Table 39.
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Intel®Server Board S2400GP TPS On-board Connector/Header Overview The server board provides one additional Type A USB port to support the installation of a USB device inside the server chassis. Table 42. Internal Type A USB Port Pin-out Pin 1 2 3 4 8.
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On-board Connector/Header Overview Intel®Server Board S2400GP TPS Note: Intel® Corporation server boards support peripheral components and can contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel®’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together.
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Intel®Server Board S2400GP TPS 9 Jumper Blocks Jumper Blocks The server boards have several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server boards. The following symbol identifies Pin 1 on each jumper block on the silkscreen: ▼ Figure 24. Jumper Blocks (J1C2, J1C5, J1E2, J2H3, J3H3, J3H4, J3H5, J3H6) Table 45.
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Jumper Blocks Intel®Server Board S2400GP TPS Jumper Name Force Update Pins 2-3 System Results BMC Firmware Force Update Mode – Enabled J3H6: BIOS Recovery 1-2 Pins 1-2 should be jumpered for normal system operation. (Default) 2-3 The main system BIOS does not boot with pins 2-3 jumpered. The system only boots from EFI-bootable recovery media with a recovery BIOS image present. J3H4: BIOS Default 1-2 These pins should have a jumper in place for normal system operation.
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Intel®Server Board S2400GP TPS Jumper Blocks power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds, and reinstall the AC power cord. Power up the system and proceed to the BIOS Setup Utility to reset the desired settings. 9.1.2 Clearing the Password 1. Power down the server. Do not unplug the power cord. 2. Open the chassis. For instructions, see your server chassis documentation. 3.
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Jumper Blocks Intel®Server Board S2400GP TPS 11. Reconnect the AC power cord and power up the server. Note: When the Force BMC Update jumper is set to the enabled position, normal BMC functionality is disabled. You should never run the server with the Force BMC Update jumper set in this position. You should only use this jumper setting when the standard firmware update process fails. When the server is running normally, this jumper must remain in the default/disabled position. 9.
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Intel®Server Board S2400GP TPS Jumper Blocks 3. Insert a bootable BIOS recovery media containing the new BIOS image files. 4. Turn on the system power. The BIOS POST screen will appear displaying the progress, and the system will boot to the EFI shell. The EFI shell then executes the Startup.nsh batch file to start the flash update process. The user should then switch off the power and return the recovery jumper to its normal position.
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Intel®Light Guided Diagnostics Intel®Server Board S2400GP TPS 10 Intel®Light Guided Diagnostics Both server boards have several on-board diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description of the location and function of each LED on the server boards. 10.1 5 V Stand-by LED Several server management features of these server boards require a 5V stand-by voltage supplied from the power supply.
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Intel®Server Board S2400GP TPS Intel®Light Guided Diagnostics 10.2 Fan Fault LEDs Fan fault LEDs are present for the two CPU fans and are located near each CPU fan header. Figure 26. Fan Fault LED Locations 10.3 CPU Fault LEDs CPU fault LEDs are present for the two CPUs and are located near each CPU fan header. 109 Revision 1.
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Intel®Light Guided Diagnostics Intel®Server Board S2400GP TPS Figure 27. CPU Fault LED Locations 10.4 System Status LED The server boards provide a System Status LED. The following figures show the location of the LED. 110 Revision 1.
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Intel®Server Board S2400GP TPS Intel®Light Guided Diagnostics Figure 28. System Status LED Location 111 Revision 1.
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Intel®Light Guided Diagnostics Intel®Server Board S2400GP TPS The bi-color (green/amber) System Status LED operates as follows: Table 46.
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Intel®Server Board S2400GP TPS Color State Amber Solid on Intel®Light Guided Diagnostics Criticality Description  Power Unit Redundancy sensor – Insufficient resources offset (indicates not enough power supplies present)  In non-sparing and non-mirroring mode if the threshold of correctable errors is crossed within the window  Correctable memory error threshold has been reached for a failing DDR3 DIMM when the system is operating in a non-redundant mode Critical, nonrecoverable – System is halted
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Intel®Light Guided Diagnostics Intel®Server Board S2400GP TPS Figure 29. DIMM Fault LEDs Location 10.6 BMC Boot/Reset Status LED Indicators During the BMC boot or BMC reset process, the System Status LED and System ID LED are used to indicate BMC boot process transitions and states. A BMC boot will occur when AC power is first applied to the system. A BMC reset will occur after: a BMC FW update, upon receiving a BMC cold reset command, and upon a BMC watchdog initiated reset.
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Intel®Server Board S2400GP TPS Intel®Light Guided Diagnostics Table 47. BMC Boot/Reset Status LED Indicators Chassis ID LED Solid Blue Solid Blue Status LED Solid Amber Solid Amber BMC in u-Boot Blink Blue 3Hz Blink Green 1Hz BMC Booting Linux* Solid Blue Solid Green End of BMC boot/reset process. Normal system operation Off Solid Green BMC Boot/Reset State BMC/Video memory test failed Both Universal Bootloader (u-Boot) images bad Comment ® Non-recoverable condition.
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Intel®Light Guided Diagnostics Intel®Server Board S2400GP TPS C. Diagnostic LED #3 G. Diagnostic LED #7 D. Diagnostic LED #4 H. Diagnostic LED #8 (MSB LED) Figure 30. POST Code Diagnostic LED Locations 116 Revision 1.
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Intel®Server Board S2400GP TPS Environmental Limits Specification 11 Environmental Limits Specification The following table defines the Intel® Server Board S2400GP operating and non-operating environmental limits. Operation of the Intel® Server Board S2400GP at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 48.
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Environmental Limits Specification Intel®Server Board S2400GP TPS building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible, if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. 11.
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Intel®Server Board S2400GP TPS Environmental Limits Specification Figure 31. Power Distribution Block Diagram 119 Revision 1.
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Environmental Limits Specification Intel®Server Board S2400GP TPS Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, you must remove AC power cord. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.  This server board supports Intel® Xeon® Processor E5-2400 product family with a Thermal Design Power (TDP) of up to and including 95 Watts.
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Intel®Server Board S2400GP TPS Appendix B: BMC Sensor Tables Appendix B: BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.
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Appendix B: BMC Sensor Tables  Intel®Server Board S2400GP TPS Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states. You can rearm the sensors manually or automatically. This column indicates the type supported by the sensor.
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Intel®Server Board S2400GP TPS Appendix B: BMC Sensor Tables Table 50.
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Appendix B: BMC Sensor Tables Sensor Name3 Physical Scrty Sensor # 04h Intel®Server Board S2400GP TPS Platform Applicability Chassis Intrusion is chassisspecific Sensor Type Physical Security 05h Event/Reading Type Sensor Specific 6Fh Sensor Specific 6Fh Digital Discrete 03h Contrib.
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Intel®Server Board S2400GP TPS Sensor Name3 Sensor # Appendix B: BMC Sensor Tables Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers BB +3.3V 16h All Voltage 02h Threshold 01h [u,l] [c,nc] BB +3.3V STBY 17h All Voltage 02h Threshold 01h [u,l] [c,nc] BB Vbat 18h All Voltage 02h Threshold 01h [u,l] [c,nc] BB +5.0V 19h All Voltage 02h Threshold 01h [u,l] [c,nc] BB +5.0V STBY 1Ah All Voltage 02h Threshold 01h [u,l] [c,nc] BB +12.
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Appendix B: BMC Sensor Tables Sensor Name3 Intel®Server Board S2400GP TPS Platform Applicability Sensor # Sensor Type Event/Reading Type Chassisspecific Fan 04h Threshold 01h Fan 04h Fan 04h – Generic 08h Generic 0Bh – Fan Tach Sensors 30h–39h Fan Present Sensors 40h–45h Fan Redundancy 4 46h – – Chassisspecific Chassisspecific – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Power Supply 08h – – Sensor Specific 6Fh – – – –
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Intel®Server Board S2400GP TPS Sensor Name3 Appendix B: BMC Sensor Tables Platform Applicability Sensor # – – Sensor Specific 6Fh – – – – – – – – 51h Chassisspecific – – – – – – – – Assert/De -assert Readable Value/Offse ts 00 - Presence OK As and De – Trig Offset A X 01 - Failure 02 – Predictive Failure 03 - A/C lost 06 – Configuration error Degraded – – – – – – – – – – – – – – – – – – – – As and De Analog R, T A X As and De Analog R, T A X As and De Analog
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Appendix B: BMC Sensor Tables Sensor Name3 Sensor # Intel®Server Board S2400GP TPS Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Intel®Server Board S2400GP TPS Appendix C: POST Code Diagnostic LED Decoder Appendix C: POST Code Diagnostic LED Decoder As an aid to assist in trouble shooting a system hang that occurs during a system’s Power-On Self Test (POST) process, the server board includes a bank of eight POST Code Diagnostic LEDs on the back edge of the server board.
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Appendix C: POST Code Diagnostic LED Decoder Intel®Server Board S2400GP TPS Note: Diag LEDs are best read and decoded when viewing the LEDs from the back of the system Table 51.
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Intel®Server Board S2400GP TPS Appendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED # #7 #6 #5 #4 #3 #2 #1 #0 62h 0 1 1 0 0 0 1 0 63h 0 1 1 0 0 0 1 1 68h 0 1 1 0 1 0 0 0 69h 0 1 1 0 1 0 0 1 6Ah 0 1 1 0 1 0 1 0 70h 0 1 1 1 0 0 0 0 71h 0 1 1 1 0 0 0 1 72h 0 1 1 1 0 0 1 0 78h 0 1 1 1 1 0 0 0 79h 0 1 1 1 1 0 0 1 90h 1 0 0 1 0 0 0 0 91h 1 0 0 1 0 0 0 1 92h 1 0 0 1 0 0 1 0 93h 1 0 0 1 0 0 1 1 94h 1 0
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Appendix C: POST Code Diagnostic LED Decoder Intel®Server Board S2400GP TPS Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED # #7 #6 #5 #4 #3 #2 #1 #0 F0h 1 1 1 1 0 0 0 0 F1h 1 1 1 1 0 0 0 1 F2h 1 1 1 1 0 0 1 0 F3h 1 1 1 1 0 0 1 1 F4h 1 1 1 1 0 1 0 0 Description PEIM which detected forced Recovery condition PEIM which detected User Recovery condition Recovery PEIM (Recovery started) Recovery PEIM (Capsule found) Recovery PEIM (Capsule
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Intel®Server Board S2400GP TPS Appendix C: POST Code Diagnostic LED Decoder LEDs, and a system halt command is executed. Fatal MRC error halts do NOT change the state of the System Status LED, and they do NOT get logged as SEL events. The following table lists all MRC fatal errors that are displayed to the Diagnostic LEDs. Table 54.
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Appendix D: POST Code Errors Intel®Server Board S2400GP TPS Appendix D: POST Code Errors Most error conditions encountered during POST are reported using POST Error Codes. These codes represent specific failures, warnings, or are informational. POST Error Codes may be displayed in the Error Manager display screen, and are always logged to the System Event Log (SEL). Logged events are available to System Management applications, including Remote and Out of Band (OOB) management.
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Intel®Server Board S2400GP TPS Appendix D: POST Code Errors Table 55.
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Appendix D: POST Code Errors Error Code 852E 852F 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 853A 853B 853C 853D 853E 853F (Go to 85C0) 8540 8541 8542 8543 8544 8545 8546 8547 8548 8549 854A 854B 854C 854D 854E 854F 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 855A 855B 855C 855D 855E 855F (Go to 85D0) 8560 8561 8562 8563 Intel®Server Board S2400GP TPS Error Message DIMM_E3 failed test/initialization DIMM_F1 failed test/initialization DIMM_F2 failed test/initialization DIMM_F3 failed test/init
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Intel®Server Board S2400GP TPS Error Code 8564 8565 8566 8567 8568 8569 856A 856B 856C 856D 856E 856F 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 857A 857B 857C 857D 857E 857F (Go to 85E0) 85C0 85C1 85C2 85C3 85C4 85C5 85C6 85C7 85C8 85C9 85CA 85CB 85CC 85CD 85CE 85CF 85D0 85D1 85D2 85D3 85D4 85D5 85D6 85D7 85D8 85D9 85DA 85DB Appendix D: POST Code Errors Error Message DIMM_B2 encountered a Serial Presence Detection (SPD) failure DIMM_B3 encountered a Serial Presence Detection (SPD) failure DIMM_C1
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Appendix D: POST Code Errors Error Code 85DC 85DD 85DE 85DF 85E0 85E1 85E2 85E3 85E4 85E5 85E6 85E7 85E8 85E9 85EA 85EB 85EC 85ED 85EE 85EF 8604 8605 8606 92A3 92A9 A000 A001 A002 A003 A100 A421 A5A0 A5A1 A6A0 Intel®Server Board S2400GP TPS Error Message DIMM_O3 disabled DIMM_P1 disabled DIMM_P2 disabled DIMM_P3 disabled DIMM_K3 encountered a Serial Presence Detection (SPD) failure DIMM_L1 encountered a Serial Presence Detection (SPD) failure DIMM_L2 encountered a Serial Presence Detection (SPD) failure D
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Intel®Server Board S2400GP TPS Beeps 4 Error Message BIOS Recovery failure Appendix D: POST Code Errors POST Progress Code NA Description BIOS recovery has failed. This typically happens so quickly after recovery us initiated that it sounds like a 2-4 beep code. The Integrated BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously.
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Appendix E: Supported Intel®Server Chassis Intel®Server Board S2400GP TPS Appendix E: Supported Intel®Server Chassis The Intel® Server Board S2400GP requires a passive processor heat sink solution when integrated in the Intel® pedestal server chassis Intel® Server Chassis P4000 series. The Intel® Server Board S2400GP supports up to 95W TDP Intel® Xeon® Processor. ® Table 58.
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Intel®Server Board S2400GP TPS Appendix E: Supported Intel®Server Chassis  Figure 33. Processor Heatsink Installation 141 Revision 1.
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Glossary Intel®Server Board S2400GP TPS Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
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Intel®Server Board S2400GP TPS Glossary Term GPIO General Purpose I/O Definition GTL Gunning Transceiver Logic GPA Guest Physical Address HSC Hot-Swap Controller HPA Host Physical Address Hz Hertz (1 cycle/second) I2C Inter-Integrated Circuit Bus IA Intel Architecture IBF Input Buffer ICH I/O Controller Hub IC MB Intelligent Chassis Management Bus IERR Internal Error IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrup
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Glossary Intel®Server Board S2400GP TPS Term Definition NIC Network Interface Controller Nm Nanometer NMI Non-maskable Interrupt NUMA Non-Uniform Memory Architecture NVSRAM Non-volatile Static Random Access Memory OBF Output Buffer OEM Original Equipment Manufacturer Ohm Unit of electrical resistance PAE Physical Address Extension PECI Platform Environment Control Interface PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area (This feature configu
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Intel®Server Board S2400GP TPS Glossary Term TDP Thermal Design Power Definition TIM Thermal Interface Material UART Universal Asynchronous Receiver/Transmitter UDIMM Unbuffered Dual In-Line Memory Module UDP User Datagram Protocol UHCI Universal Host Controller Interface URS Unified Retention System UTC Universal time coordinate VID Voltage Identification VLSI Very-large-scale integration VRD Voltage Regulator Down VT Virtualization Technology Word 16-bit quantity ZIF Zero Ins
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Reference Documents Intel®Server Board S2400GP TPS Reference Documents See the following documents for additional information:  Advanced Configuration and Power Interface Specification, Revision 3.0, http://www.acpi.info/.  Intelligent Platform Management Bus Communications Protocol Specification, Version 1.0. 1998. Intel Corporation, Hewlett-Packard* Company, NEC* Corporation, Dell* Computer Corporation.  Intelligent Platform Management Interface Specification, Version 2.0. 2004.