Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
95
Table 85. 2Ch: GVD.SSID – Subsystem Identifiers
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
2Ch
Message Bus Port:
06h
Register Address: 0Bh
Bit Range Default Access Acronym Description
31 0 0h WOARnROAW
SUBSYSTEM_ID
ENTIFIERS
The value in this field is programmed by the system BIOS. According to
the PCI spec, only the BIOS can write it, and only once after reset. After
the first write, this register becomes read-only. The content of this
register may also be read (not written) from the Device 0 subsystem
register address.
Table 86. 34h: GVD.CAPPOINT – Capabilities Pointer
Size: 32 bit Default: 000000D0h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
34h
Message Bus Port:
06h
Register Address: 0Dh
Bit Range Default Access Acronym Description
31 :8
000000
h
RO RESERVED Reserved
7:0 D0h RO
CAPABILITIES_
POINTER
The first item in the capabilities list is at address D0h.
Table 87. 3Ch: GVD.INTR – Interrupt
Size: 32 bit Default: 00000100h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
3Ch
Message Bus Port:
06h
Register Address: 0Fh
Bit Range Default Access Acronym Description
31 :16 0000h RO RESERVED Reserved
15 :8 01h RO
INTERRUPT_PI
N
IPIN: Value indicates which interrupt pin this device uses. This field is
hard coded to 1h since the processor Device 2 is a single function device.
The PCI spec requires that it use INTA#.
7 :0 00h RW
INTERRUPT_LI
NE
ILIN: BIOS written value to communicate interrupt line routing
information to the device driver.